 |
trngpsv
Vitis Drivers API Documentation
|
|
trngpsv
Vitis Drivers API Documentation
|
Macros | |
Register definitions | |
| #define | TRNG_STATUS 0x00000004U |
| TRNG status offset. More... | |
| #define | TRNG_STATUS_QCNT_MASK 0x00000e00U |
| TRNG QCNT mask. More... | |
| #define | TRNG_STATUS_CERTF_MASK 0x00000008U |
| TRNG CERTF mask. More... | |
| #define | TRNG_STATUS_DTF_MASK 0x00000002U |
| TRNG DTF mask. More... | |
| #define | TRNG_STATUS_DONE_MASK 0x00000001U |
| TRNG status done mask. More... | |
| #define | TRNG_CTRL 0x00000008U |
| TRNG control offset. More... | |
| #define | TRNG_CTRL_EUMODE_MASK 0x00000100U |
| Entropy data collection mode mask. More... | |
| #define | TRNG_CTRL_PRNGMODE_MASK 0x00000080U |
| Pseudo random number mode mask. More... | |
| #define | TRNG_CTRL_PRNGSTART_MASK 0x00000020U |
| PRNG start mask. More... | |
| #define | TRNG_CTRL_PRNGXS_MASK 0x00000008U |
| PRNG seed source mask. More... | |
| #define | TRNG_CTRL_TRSSEN_MASK 0x00000004U |
| True random seed source enable mask. More... | |
| #define | TRNG_CTRL_PRNGSRST_MASK 0x00000001U |
| PRNG soft reset mask. More... | |
| #define | TRNG_EXT_SEED_0 0x00000040U |
| TRNG external seed 0 offset. More... | |
| #define | TRNG_PER_STRNG_0 0x00000080U |
| Below registers are not directly referenced in driver but are accessed accessed with offset from TRNG_EXT_SEED_0. More... | |
| #define | TRNG_CORE_OUTPUT 0x000000C0U |
| Below registers are not directly referenced in driver but are accessed accessed with offset from TRNG_PER_STRNG_0. More... | |
| #define | TRNG_RESET 0x000000D0U |
| TRNG reset offset. More... | |
| #define | TRNG_RESET_VAL_MASK 0x00000001U |
| TRNG default reset value. More... | |
| #define | TRNG_OSC_EN 0x000000D4U |
| TRNG oscillator enable offset. More... | |
| #define | TRNG_OSC_EN_VAL_MASK 0x00000001U |
| TRNG default oscillator enable value. More... | |