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mipi_tx_phy
Vitis Drivers API Documentation
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mipi_tx_phy
Vitis Drivers API Documentation
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Macros | |
| #define | XMIPI_TX_PHY_HW_H_ |
| Prevent circular inclusions by using protection macros. More... | |
Device registers | |
Register sets of MIPI_TX_PHY | |
| #define | XMIPI_TX_PHY_CTRL_REG_OFFSET 0x00000000 |
| Control Register. More... | |
| #define | XMIPI_TX_PHY_VERSION_REG_OFFSET 0x00000004 |
| Core Version Register. More... | |
| #define | XMIPI_TX_PHY_INIT_TIMER_REG_OFFSET 0x00000008 |
| Initialization Timer Register. More... | |
| #define | XMIPI_TX_PHY_HSTIMEOUT_REG_OFFSET 0x00000010 |
| Watchdog timeout in HS mode Register. More... | |
| #define | XMIPI_TX_PHY_ESCTIMEOUT_REG_OFFSET 0x00000014 |
| Goto Stop state on timeout timer Register. More... | |
| #define | XMIPI_TX_PHY_CLSTATUS_REG_OFFSET 0x00000018 |
| Clk lane PHY error Status Register. More... | |
| #define | XMIPI_TX_PHY_DL0STATUS_REG_OFFSET 0x0000001C |
| Data lane 0 PHY error Status Register. More... | |
| #define | XMIPI_TX_PHY_DL1STATUS_REG_OFFSET 0x00000020 |
| Data lane 1 PHY error Status Register. More... | |
| #define | XMIPI_TX_PHY_DL2STATUS_REG_OFFSET 0x00000024 |
| Data lane 2 PHY error Status Register. More... | |
| #define | XMIPI_TX_PHY_DL3STATUS_REG_OFFSET 0x00000028 |
| Data lane 3 PHY error Status Register. More... | |
| #define | XMIPI_TX_PHY_PROG_SEQ_CTRL_OFFSET 0x00000038 |
| Prog Seq Control Register. More... | |
| #define | XMIPI_TX_PHY_PROG_SEQ_DATA0_OFFSET 0x0000003C |
| Prog Seq Data Register 0. More... | |
| #define | XMIPI_TX_PHY_PROG_SEQ_DATA1_OFFSET 0x00000040 |
| Prog Seq Data Register 1. More... | |
Bitmasks and offsets of XMIPI_TX_PHY_CTRL_REG_OFFSET register | |
This register is used for the enabling/disabling and resetting the MIPI_TX_PHY | |
| #define | XMIPI_TX_PHY_CTRL_REG_SOFTRESET_MASK 0x00000001 |
| Soft Reset. More... | |
| #define | XMIPI_TX_PHY_CTRL_REG_PHYEN_MASK 0x00000002 |
| Enable/Disable controller. More... | |
| #define | XMIPI_TX_PHY_CTRL_REG_SOFTRESET_OFFSET 0 |
| Bit offset for Soft Reset. More... | |
| #define | XMIPI_TX_PHY_CTRL_REG_PHYEN_OFFSET 1 |
| Bit offset for PHY Enable. More... | |
| #define | XMIPI_TX_PHY_PROG_SEQ_EN_MASK 0x1 |
| Enable/Disable Prog Seq. More... | |
Bitmasks and offsets of XMIPI_TX_PHY_INIT_REG_OFFSET register | |
This register is used for lane Initialization. Recommended to use 1ms or longer in for TX mode and 200us-500us for RX mode | |
| #define | XMIPI_TX_PHY_INIT_REG_VAL_MASK 0xFFFFFFFF |
| Init Timer value in ns. More... | |
| #define | XMIPI_TX_PHY_INIT_REG_VAL_OFFSET 0 |
| Bit offset for Init Timer. More... | |
Bitmask and offset of XMIPI_TX_PHY_HSTIMEOUT_REG_OFFSET register | |
This register is used to program watchdog timer in high speed mode. Default value is 65541. Valid range 1000-65541. | |
| #define | XMIPI_TX_PHY_HSTIMEOUT_REG_TIMEOUT_MASK 0xFFFFFFFF |
| HS_TX_TIMEOUT Received. More... | |
| #define | XMIPI_TX_PHY_HSTIMEOUT_REG_TIMEOUT_OFFSET 0 |
| Bit offset for Timeout. More... | |
Bitmask and offset of XMIPI_TX_PHY_ESCTIMEOUT_REG_OFFSET register | |
This register contains Rx Data Lanes timeout for watchdog timer in escape mode. | |
| #define | XMIPI_TX_PHY_ESCTIMEOUT_REG_VAL_MASK 0xFFFFFFFF |
| Escape Timout Value. More... | |
| #define | XMIPI_TX_PHY_ESCTIMEOUT_REG_VAL_OFFSET 0 |
| Bit offset for Escape Timeout. More... | |
Bitmask and offset of XMIPI_TX_PHY_CLSTATUS_REG_OFFSET register | |
This register contains the clock lane status and state machine control. | |
| #define | XMIPI_TX_PHY_CLSTATUS_REG_ERRCTRL_MASK 0x00000020 |
| Clock lane control error. More... | |
| #define | XMIPI_TX_PHY_CLSTATUS_REG_STOPSTATE_MASK 0x00000010 |
| Clock lane stop state. More... | |
| #define | XMIPI_TX_PHY_CLSTATUS_REG_INITDONE_MASK 0x00000008 |
| Initialization done bit. More... | |
| #define | XMIPI_TX_PHY_CLSTATUS_REG_ULPS_MASK 0x00000004 |
| Set in ULPS mode. More... | |
| #define | XMIPI_TX_PHY_CLSTATUS_REG_MODE_MASK 0x00000003 |
| Low, High, Esc mode. More... | |
| #define | XMIPI_TX_PHY_CLSTATUS_ALLMASK |
| #define | XMIPI_TX_PHY_CLSTATUS_REG_ERRCTRL_OFFSET 5 |
| Bit offset for Control Error on Clock. More... | |
| #define | XMIPI_TX_PHY_CLSTATUS_REG_STOPSTATE_OFFSET 4 |
| Bit offset for Stop State on Clock. More... | |
| #define | XMIPI_TX_PHY_CLSTATUS_REG_INITDONE_OFFSET 3 |
| Bit offset for Initialization Done. More... | |
| #define | XMIPI_TX_PHY_CLSTATUS_REG_ULPS_OFFSET 2 |
| Bit offset for ULPS. More... | |
| #define | XMIPI_TX_PHY_CLSTATUS_REG_MODE_OFFSET 0 |
| Bit offset for Mode bits. More... | |
Bitmasks and offsets of XMIPI_TX_PHY_DLxSTATUS_REG_OFFSET register | |
This register contains the data lanes status | |
| #define | XMIPI_TX_PHY_DLXSTATUS_REG_PACKETCOUNT_MASK 0xFFFF0000 |
| Packet Count. More... | |
| #define | XMIPI_TX_PHY_DLXSTATUS_REG_CALIB_STATUS_MASK 0x00000100 |
| Calib status. More... | |
| #define | XMIPI_TX_PHY_DLXSTATUS_REG_CALIB_COMPLETE_MASK 0x00000080 |
| Calib complete. More... | |
| #define | XMIPI_TX_PHY_DLXSTATUS_REG_STOP_MASK 0x00000040 |
| Stop State on data lane. More... | |
| #define | XMIPI_TX_PHY_DLXSTATUS_REG_ESCABRT_MASK 0x00000020 |
| Set on Data Lane Esc timeout occurs. More... | |
| #define | XMIPI_TX_PHY_DLXSTATUS_REG_HSABRT_MASK 0x00000010 |
| Set on Data Lane HS timeout. More... | |
| #define | XMIPI_TX_PHY_DLXSTATUS_REG_INITDONE_MASK 0x00000008 |
| Set after initialization. More... | |
| #define | XMIPI_TX_PHY_DLXSTATUS_REG_ULPS_MASK 0x00000004 |
| Set when MIPI_TX_PHY in ULPS mode. More... | |
| #define | XMIPI_TX_PHY_DLXSTATUS_REG_MODE_MASK 0x00000003 |
| Control Mode (Esc, Low, High) of Data Lane. More... | |
| #define | XMIPI_TX_PHY_DLXSTATUS_ALLMASK |
| #define | XMIPI_TX_PHY_DLXSTATUS_REG_PACKCOUNT_OFFSET 16 |
| Bit offset packet count. More... | |
| #define | XMIPI_TX_PHY_DLXSTATUS_REG_CALIB_STATUS_OFFSET 8 |
| Bit offset calib status. More... | |
| #define | XMIPI_TX_PHY_DLXSTATUS_REG_CALIB_COMPLETE_OFFSET 7 |
| Bit offset Calib complete. More... | |
| #define | XMIPI_TX_PHY_DLXSTATUS_REG_STOP_OFFSET 6 |
| Bit offset for Stop State. More... | |
| #define | XMIPI_TX_PHY_DLXSTATUS_REG_ESCABRT_OFFSET 5 |
| Bit offset for Escape Abort. More... | |
| #define | XMIPI_TX_PHY_DLXSTATUS_REG_HSABRT_OFFSET 4 |
| Bit offset for High Speed Abort. More... | |
| #define | XMIPI_TX_PHY_DLXSTATUS_REG_INITDONE_OFFSET 3 |
| Bit offset for Initialization done. More... | |
| #define | XMIPI_TX_PHY_DLXSTATUS_REG_ULPS_OFFSET 2 |
| Bit offset for ULPS. More... | |
| #define | XMIPI_TX_PHY_DLXSTATUS_REG_MODE_OFFSET 0 |
| Bit offset for Modes. More... | |
Bitmask and offset of XMIPI_TX_PHY_HSSETTLE_REG_OFFSET register | |
This register is used to program the HS SETTLE register. Default value is 135 + 10UI. | |
| #define | XMIPI_TX_PHY_HSSETTLE_REG_TIMEOUT_MASK 0x1FF |
| HS_SETTLE value. More... | |
| #define | XMIPI_TX_PHY_HSSETTLE_REG_TIMEOUT_OFFSET 0 |
| Bit offset for HS_SETTLE. More... | |