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i3c
Vitis Drivers API Documentation
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i3c
Vitis Drivers API Documentation
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Macros | |
| #define | XI3C_HW_H_ |
| < prevent circular inclusions More... | |
| #define | XI3C_BASEADDR 0x0 |
| AXI_I3C0 Base Address #define XI3C_BASEADDR 0x80000000. More... | |
| #define | XI3C_VERSION_OFFSET 0x00 |
| Register offsets for the XI3c device. More... | |
| #define | XI3C_RESET_OFFSET 0x04 |
| Soft Reset Register. More... | |
| #define | XI3C_CR_OFFSET 0x08 |
| Control Register. More... | |
| #define | XI3C_ADDRESS_OFFSET 0x0C |
| Target Address Register. More... | |
| #define | XI3C_SR_OFFSET 0x10 |
| Status Register. More... | |
| #define | XI3C_INTR_STATUS_OFFSET 0x14 |
| Status Event Register. More... | |
| #define | XI3C_INTR_RE_OFFSET 0x18 |
| Status Event Enable(Rising Edge) Register. More... | |
| #define | XI3C_INTR_FE_OFFSET 0x1C |
| Status Event Enable(Falling Edge) Register. More... | |
| #define | XI3C_CMD_FIFO_OFFSET 0x20 |
| I3C Command FIFO Register. More... | |
| #define | XI3C_WR_FIFO_OFFSET 0x24 |
| I3C Write Data FIFO Register. More... | |
| #define | XI3C_RD_FIFO_OFFSET 0x28 |
| I3C Read Data FIFO Register. More... | |
| #define | XI3C_RESP_STATUS_FIFO_OFFSET 0x2C |
| I3C Response status FIFO Register. More... | |
| #define | XI3C_FIFO_LVL_STATUS_OFFSET 0x30 |
| I3C CMD & WR FIFO LVL Register. More... | |
| #define | XI3C_FIFO_LVL_STATUS_1_OFFSET 0x34 |
| I3C RESP & RD FIFO LVL Register. More... | |
| #define | XI3C_SCL_HIGH_TIME_OFFSET 0x38 |
| I3C SCL HIGH Register. More... | |
| #define | XI3C_SCL_LOW_TIME_OFFSET 0x3C |
| I3C SCL LOW Register. More... | |
| #define | XI3C_SDA_HOLD_TIME_OFFSET 0x40 |
| I3C SDA HOLD Register. More... | |
| #define | XI3C_BUS_IDLE_OFFSET 0x44 |
| I3C CONTROLLER BUS IDLE Register. More... | |
| #define | XI3C_TSU_START_OFFSET 0x48 |
| I3C START SETUP Register. More... | |
| #define | XI3C_THD_START_OFFSET 0x4C |
| I3C START HOLD Register. More... | |
| #define | XI3C_TSU_STOP_OFFSET 0x50 |
| I3C STOP Setup Register. More... | |
| #define | XI3C_OD_SCL_HIGH_TIME_OFFSET 0x54 |
| I3C OD SCL HIGH Register. More... | |
| #define | XI3C_OD_SCL_LOW_TIME_OFFSET 0x58 |
| I3C OD SCL LOW Register. More... | |
| #define | XI3C_TARGET_ADDR_BCR 0x60 |
| I3C Target dynamic Address and BCR Register. More... | |
| #define | XI3C_MWL_MRL 0x74 |
| Maximum Write and Max Read length. More... | |
| #define | XI3C_EVENT 0x78 |
| Target events. More... | |
| #define | XI3C_GETMXDS 0x80 |
| Target Device Max Data Speed. More... | |
| #define | XI3C_GETSTATUS 0x84 |
| Target Device current Status. More... | |
| #define | XI3C_GETCAPS_REG0 0x88 |
| Target Device Format 1 Capabilities. More... | |
| #define | XI3C_GETCAPS_REG1 0x8c |
| Target Device Format 2 Capabilities. More... | |
| #define | XI3C_CON_RD_BYTE_COUNT 0x90 |
| Read byte count register. More... | |
Version Register mask(s) | |
| #define | XI3C_INTERNAL_REVISION_MASK 0x0000000F |
| BITS 3:0 - Internal revision. More... | |
| #define | XI3C_CORE_PATCH_REVISION_MASK 0x000000F0 |
| BITS 7:4 - Patch revision. More... | |
| #define | XI3C_CORE_REVISION_NUM_MASK 0x0000FF00 |
| BITS 15:8 - Revision number. More... | |
| #define | XI3C_CORE_VERSION_MINOR_MASK 0x00FF0000 |
| BITS 23:16 - Minor version. More... | |
| #define | XI3C_CORE_VERSION_MAJOR_MASK 0xFF000000 |
| BITS 31:24 - Major version. More... | |
| #define | XI3C_CORE_REVISION_NUM_SHIFT 8 |
| Revision number shift. More... | |
Reset Register mask(s) | |
| #define | XI3C_SOFT_RESET_MASK 0x00000001 |
| BIT 0 - Reset. More... | |
| #define | XI3C_CMD_FIFO_RESET_MASK 0x00000002 |
| BIT 1 - Cmd fifo reset. More... | |
| #define | XI3C_WR_FIFO_RESET_MASK 0x00000004 |
| BIT 2 - Write fifo reset. More... | |
| #define | XI3C_RD_FIFO_RESET_MASK 0x00000008 |
| BIT 3 - Read fifo reset. More... | |
| #define | XI3C_RESP_FIFO_RESET_MASK 0x00000010 |
| BIT 4 - Response fifo reset. More... | |
| #define | XI3C_ALL_FIFOS_RESET_MASK 0x0000001E |
| BIT 1 to 4 - All fifos reset. More... | |
Control Register (CR) mask(s) | |
| #define | XI3C_CR_EN_MASK 0x00000001 |
| BIT 0 - Core Enable. More... | |
| #define | XI3C_CR_ABORT_MASK 0x00000002 |
| BIT 1 - Abort Transaction. More... | |
| #define | XI3C_CR_RESUME_MASK 0x00000004 |
| BIT 2 - Resume Operation. More... | |
| #define | XI3C_CR_IBI_MASK 0x00000008 |
| BIT 3 - IBI Enable. More... | |
| #define | XI3C_CR_HJ_MASK 0x00000010 |
| BIT 4 - Hot Join Enable. More... | |
| #define | XI3C_CR_ACCEPT_CTRL_ROLE_REQ 0x00000020 |
| BIT 5 - Generate ACK for secondary controller role request IBI. More... | |
Status Register (SR) mask(s) | |
| #define | XI3C_SR_BUS_BUSY_MASK 0x00000001 |
| BIT 0 - Bus Busy. More... | |
| #define | XI3C_SR_CLK_STALL_MASK 0x00000002 |
| BIT 1 - Clock Stall. More... | |
| #define | XI3C_SR_CMD_FULL_MASK 0x00000004 |
| BIT 2 - Cmd Fifo Full. More... | |
| #define | XI3C_SR_RESP_FULL_MASK 0x00000008 |
| BIT 3 - Resp Fifo Full. More... | |
| #define | XI3C_SR_RESP_NOT_EMPTY_MASK 0x00000010 |
| BIT 4 - Resp Fifo not empty. More... | |
| #define | XI3C_SR_WR_FULL_MASK 0x00000020 |
| BIT 5 - Write Fifo Full. More... | |
| #define | XI3C_SR_RD_FULL_MASK 0x00000040 |
| BIT 6 - Read Fifo Full. More... | |
| #define | XI3C_SR_IBI_MASK 0x00000080 |
| BIT 7 - IBI. More... | |
| #define | XI3C_SR_HJ_MASK 0x00000100 |
| BIT 8 - Hot join. More... | |
| #define | XI3C_SR_CTRL_ROLE_REQUEST_MASK 0x00000200 |
| BIT 9 - Received control role request. More... | |
| #define | XI3C_SR_ERROR_TYPE_CE3_MASK 0x00000400 |
| BIT 10 - This field will be set if there is no START coming from the new Controller that has took over the Role. More... | |
| #define | XI3C_SR_RETURN_ROLE_REQ_ACK_MASK 0x00000800 |
| BIT 11 - Received ACK on controller role request back. More... | |
| #define | XI3C_SR_RD_FIFO_ALMOST_FULL_MASK 0x00001000 |
| BIT 12 - Read Fifo almost Full. More... | |
| #define | XI3C_SR_CMD_FIFO_NOT_EMPTY_MASK 0x00002000 |
| BIT 13 - CMD FIFO empty. More... | |
| #define | XI3C_SR_WR_FIFO_NOT_EMPTY_MASK 0x00004000 |
| BIT 14 - Write FIFO empty. More... | |
| #define | XI3C_SR_RD_FIFO_NOT_EMPTY_MASK 0x00008000 |
| BIT 15 - Read FIFO empty. More... | |
| #define | XI3C_SR_SLV_DYNC_ADDR_DONE_MASK 0x00080000 |
| BIT 19 - Dynamic address assigned to slave. More... | |
Status Register (SR) Shifts(s) | |
| #define | XI3C_SR_BUS_BUSY_SHIFT 0 |
| BIT 0 - Bus Busy. More... | |
| #define | XI3C_SR_CLK_STALL_SHIFT 1 |
| BIT 1 - Clock Stall. More... | |
| #define | XI3C_SR_CMD_FULL_SHIFT 2 |
| BIT 2 - Cmd Fifo Full. More... | |
| #define | XI3C_SR_RESP_FULL_SHIFT 3 |
| BIT 3 - Resp Fifo Full. More... | |
| #define | XI3C_SR_RESP_NOT_EMPTY_SHIFT 4 |
| BIT 4 - Resp Fifo not empty. More... | |
| #define | XI3C_SR_WR_FULL_SHIFT 5 |
| BIT 5 - Write Fifo Full. More... | |
| #define | XI3C_SR_RD_FULL_SHIFT 6 |
| BIT 6 - Read Fifo Full. More... | |
| #define | XI3C_SR_SLV_DYNC_ADDR_DONE_SHIFT 19 |
| BIT 19 - Dynamic address assigned to slave. More... | |
response and other mask(s) | |
| #define | XI3C_RESP_ID_MASK 0x0000000F |
| #define | XI3C_RESP_RW_MASK 0x00000010 |
| #define | XI3C_RESP_CODE_MASK 0x000001E0 |
| #define | XI3C_RESP_BYTES_MASK 0x001FFE00 |
| #define | XI3C_SLV_RESP_CCC_MASK 0x1FE00000 |
| #define | XI3C_SLV_RESP_7E_FRAME_MASK 0x20000000 |
| #define | XI3C_MRL_MASK 0x0FFF0000 |
| #define | XI3C_GRP_ADDR_MASK 0x0000FF00 |
response and other shift(s) | |
| #define | XI3C_RESP_TID_SHIFT 0 |
| #define | XI3C_RESP_RW_SHIFT 4 |
| #define | XI3C_RESP_CODE_SHIFT 5 |
| #define | XI3C_RESP_BYTES_SHIFT 9 |
| #define | XI3C_RESP_LVL_SHIFT 16 |
| #define | XI3C_SLV_RESP_CCC_SHIFT 21 |
| #define | XI3C_SLV_RESP_7E_FRAME_SHIFT 29 |
| #define | XI3C_CMD_LVL_SHIFT 16 |
| #define | XI3C_MRL_SHIFT 16 |
| #define | XI3C_MWL_MRL_MSB_SHIFT 8 |
| #define | XI3C_GRP_ADDR_SHIFT 8 |
| #define | XI3C_GETSTATUS_FORMAT2_SHIFT 16 |
| #define | XI3C_GETMXDS_FORMAT3_DATA_SHIFT 16 |
| #define | XI3C_CAPS4_SHIFT 24 |
| #define | XI3C_CAPS3_SHIFT 16 |
| #define | XI3C_CAPS2_SHIFT 8 |
bit masks | |
| #define | XI3C_1BIT_MASK 0x00000001 |
| #define | XI3C_2BITS_MASK 0x00000003 |
| #define | XI3C_3BITS_MASK 0x00000007 |
| #define | XI3C_4BITS_MASK 0x0000000F |
| #define | XI3C_5BITS_MASK 0x0000001F |
| #define | XI3C_6BITS_MASK 0x0000003F |
| #define | XI3C_7BITS_MASK 0x0000007F |
| #define | XI3C_8BITS_MASK 0x000000FF |
| #define | XI3C_9BITS_MASK 0x000001FF |
| #define | XI3C_10BITS_MASK 0x000003FF |
| #define | XI3C_11BITS_MASK 0x000007FF |
| #define | XI3C_12BITS_MASK 0x00000FFF |
| #define | XI3C_13BITS_MASK 0x00001FFF |
| #define | XI3C_14BITS_MASK 0x00003FFF |
| #define | XI3C_15BITS_MASK 0x00007FFF |
| #define | XI3C_16BITS_MASK 0x0000FFFF |
| #define | XI3C_17BITS_MASK 0x0001FFFF |
| #define | XI3C_18BITS_MASK 0x0003FFFF |
| #define | XI3C_19BITS_MASK 0x0007FFFF |
| #define | XI3C_20BITS_MASK 0x000FFFFF |
| #define | XI3C_MSB_8BITS_MASK 0x0000FF00 |
| #define | XI3C_MSB_16BITS_MASK 0xFFFF0000 |
interrupt Register (INTR) mask(s) | |
| #define | XI3C_INTR_BUS_BUSY_MASK 0x00000001 |
| BIT 0 - Bus Busy. More... | |
| #define | XI3C_INTR_CLK_STALL_MASK 0x00000002 |
| BIT 1 - Clock Stall. More... | |
| #define | XI3C_INTR_CMD_FULL_MASK 0x00000004 |
| BIT 2 - Cmd Fifo Full. More... | |
| #define | XI3C_INTR_RESP_FULL_MASK 0x00000008 |
| BIT 3 - Resp Fifo Full. More... | |
| #define | XI3C_INTR_RESP_NOT_EMPTY_MASK 0x00000010 |
| BIT 4 - Resp Fifo not empty. More... | |
| #define | XI3C_INTR_WR_FIFO_ALMOST_FULL_MASK 0x00000020 |
| BIT 5 - Write Fifo Full. More... | |
| #define | XI3C_INTR_RD_FULL_MASK 0x00000040 |
| BIT 6 - Read Fifo Full. More... | |
| #define | XI3C_ALL_INTR_MASK 0x0000007F |
| 6:0 BITS More... | |
| #define | XI3C_INTR_IBI_MASK 0x00000080 |
| BIT 7 - IBI. More... | |
| #define | XI3C_INTR_HJ_MASK 0x00000100 |
| BIT 8 - Hot join. More... | |
| #define | XI3C_INTR_CTRL_ROLE_REQUEST_MASK 0x00000200 |
| BIT 9 - Received control role request. More... | |
| #define | XI3C_INTR_ERROR_TYPE_CE3_MASK 0x00000400 |
| BIT 10 - This field will be set if there is no START coming from the new Controller that has took over the Role. More... | |
| #define | XI3C_INTR_RETURN_ROLE_REQ_ACK_MASK 0x00000800 |
| BIT 11 - Received ACK on controller role request back. More... | |
| #define | XI3C_INTR_RD_FIFO_ALMOST_FULL_MASK 0x00001000 |
| BIT 12 - Read Fifo almost Full. More... | |
| #define | XI3C_INTR_CMD_FIFO_NOT_EMPTY_MASK 0x00002000 |
| BIT 13 - CMD FIFO empty. More... | |
| #define | XI3C_INTR_WR_FIFO_NOT_EMPTY_MASK 0x00004000 |
| BIT 14 - Write FIFO empty. More... | |
| #define | XI3C_INTR_RD_FIFO_NOT_EMPTY_MASK 0x00008000 |
| BIT 15 - Read FIFO empty. More... | |
| #define | XI3c_ReadReg(BaseAddress, RegOffset) XI3c_In32((BaseAddress) + (u32)(RegOffset)) |
| Read an I3C register. More... | |
| #define | XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue) XI3c_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue)) |
| Write an I3C register. More... | |
| #define | XI3c_WrFifoLevel(InstancePtr) |
| Read WR FIFO LEVEL. More... | |
| #define | XI3c_CmdFifoLevel(InstancePtr) |
| Read CMD FIFO LEVEL. More... | |
| #define | XI3c_RdFifoLevel(InstancePtr) |
| Read RD FIFO LEVEL. More... | |
| #define | XI3c_RespFifoLevel(InstancePtr) |
| Read RESP FIFO LEVEL. More... | |
| #define | XI3c_RxFifoNotEmpty(InstancePtr) |
| Check Read FIFO empty status. More... | |
| #define | XI3c_RespFifoNotEmpty(InstancePtr) |
| Check Response FIFO empty status. More... | |
| #define | XI3c_EnableREInterrupts(BaseAddress, IntrMask) |
| Enable Raising edge interrupts. More... | |
| #define | XI3c_EnableFEInterrupts(BaseAddress, IntrMask) |
| Enable Faling edge interrupts. More... | |
| #define | XI3c_DisableREInterrupts(BaseAddress, IntrMask) |
| Disable raising edge interrupts. More... | |
| #define | XI3c_DisableFEInterrupts(BaseAddress, IntrMask) |
| Disable faling edge interrupts. More... | |
| #define | XI3c_DisableAllREInterrupts(BaseAddress) |
| Disable all raising edge interrupts. More... | |
| #define | XI3c_DisableAllFEInterrupts(BaseAddress) |
| Disable all faling edge interrupts. More... | |
| #define | XI3c_FillSlaveSendCount(InstancePtr, ByteCount) |
| Fill Slave send byte count value. More... | |
| #define | XI3c_ClearGrpAddr(InstancePtr) |
| Clear the group address of target. More... | |
| #define | XI3c_GetMWL(InstancePtr) |
| Read Maximum write length. More... | |
| #define | XI3c_GetMRL(InstancePtr) |
| Read Maximum read length. More... | |