i2stx
Vitis Drivers API Documentation
Data Structures | Macros | Enumerations | Functions
Overview

Data Structures

struct  XI2s_Tx_LogItem
 This structure is used to store log events. More...
 
struct  XI2s_Tx_Log
 The I2s Transmitter Log buffer. More...
 

Macros

#define XI2s_Tx_GetMaxChannels(InstancePtr)
 This macro reads the maximum number of I2S channels available. More...
 
#define XI2s_Tx_IsI2sMaster(InstancePtr)
 This macro returns the I2S operating mode. More...
 

Enumerations

enum  XI2s_Tx_ChannelId {
  XI2S_TX_CHID0 = 0, XI2S_TX_CHID1, XI2S_TX_CHID2, XI2S_TX_CHID3,
  XI2S_TX_NUM_CHANNELS
}
 These constants specify different channel ID's. More...
 

Functions

int XI2s_Tx_CfgInitialize (XI2s_Tx *InstancePtr, XI2stx_Config *CfgPtr, UINTPTR EffectiveAddr)
 This function initializes the I2S Transmitter. More...
 
void XI2s_Tx_Enable (XI2s_Tx *InstancePtr, u8 Enable)
 This function enables/disables the I2s Transmitter. More...
 
void XI2s_Tx_IntrEnable (XI2s_Tx *InstancePtr, u32 Mask)
 This function enables the specified interrupt of the I2s Transmitter. More...
 
void XI2s_Tx_IntrDisable (XI2s_Tx *InstancePtr, u32 Mask)
 This function disables the specified interrupt of the I2s Transmitter. More...
 
int XI2s_Tx_SetChMux (XI2s_Tx *InstancePtr, XI2s_Tx_ChannelId ChID, XI2s_Tx_ChMuxInput InputSource)
 This function sets the input source for the specified I2s channel. More...
 
u32 XI2s_Tx_SetSclkOutDiv (XI2s_Tx *InstancePtr, u32 MClk, u32 Fs)
 This function calculates the SCLK Output divider value of the I2S timing generator. More...
 
void XI2s_Tx_GetAesChStatus (XI2s_Tx *InstancePtr, u8 *AesChStatusBuf)
 This function gets the captured AES Channel Status bits. More...
 
void XI2s_Tx_ClrAesChStatRegs (XI2s_Tx *InstancePtr)
 This function clears the captured AES Channel Status bits. More...
 
void XI2s_Tx_JustifyEnable (XI2s_Tx *InstancePtr, u8 Enable)
 This function enables/disables the justification. More...
 
void XI2s_Tx_Justify (XI2s_Tx *InstancePtr, XI2s_Tx_Justification Justify)
 This function is to enable right/left justification. More...
 
void XI2s_Tx_ReslveAesChStat (u8 I2stx_SrcBuf[])
 This function reads the array I2stx_SrcBuf which has the values of all the I2S Transmitter AES status registers, extracts the required bits and prints them. More...
 
void XI2s_Tx_LogWrite (XI2s_Tx *InstancePtr, XI2s_Tx_LogEvt Event, u8 Data)
 This function writes I2S Transmitter logs into the buffer. More...
 
XI2s_Tx_LogItem * XI2s_Tx_LogRead (XI2s_Tx *InstancePtr)
 This function returns the next item in the logging buffer. More...
 
void XI2s_Tx_LogReset (XI2s_Tx *InstancePtr)
 This function clears the contents of the logging buffer. More...
 
void XI2s_Tx_LogDisplay (XI2s_Tx *InstancePtr)
 This function prints the contents of the logging buffer. More...
 
void XI2s_Tx_IntrHandler (void *InstancePtr)
 This function is the interrupt handler for the I2S Transmitter driver. More...
 
int XI2s_Tx_SetHandler (XI2s_Tx *InstancePtr, XI2s_Tx_HandlerType HandlerType, XI2s_Tx_Callback FuncPtr, void *CallbackRef)
 This function installs an asynchronous callback function for the given HandlerType: More...
 
int XI2s_Tx_SelfTest (XI2s_Tx *InstancePtr)
 Runs a self-test on the driver/device. More...
 
XI2stx_Config * XI2s_Tx_LookupConfig (u16 DeviceId)
 This function returns a reference to an XI2stx_Config structure based on the core id, DeviceId. More...
 

XI2S_Tx_Handlertype

enum  XI2s_Tx_HandlerType {
  XI2S_TX_HANDLER_AES_BLKCMPLT = 0, XI2S_TX_HANDLER_AES_BLKSYNCERR, XI2S_TX_HANDLER_AES_CHSTSUPD, XI2S_TX_HANDLER_AUD_UNDRFLW,
  XI2S_TX_NUM_HANDLERS
}
 these constants specify different types of handlers and is used to differentiate interrupt requests from the I2s Transmitter peripheral. More...
 

AES Status and Register Masks and Shifts.For formats/line protocols

check the AES Standard specifications document.

#define XI2S_TX_AES_STS_USE_OF_CH_STS_BLK_SHIFT   (0)
 Use of Channel Status Block bit shift. More...
 
#define XI2S_TX_AES_STS_USE_OF_CH_STS_BLK_MASK   (1 << XI2S_TX_AES_STS_USE_OF_CH_STS_BLK_SHIFT)
 Use of Channel Status Block mask. More...
 
#define XI2S_TX_AES_STS_LINEAR_PCM_ID_SHIFT   (1)
 Linear PCM Identification bit shift. More...
 
#define XI2S_TX_AES_STS_LINEAR_PCM_ID_MASK   (1 << XI2S_TX_AES_STS_LINEAR_PCM_ID_SHIFT)
 Linear PCM Identification mask. More...
 
#define XI2S_TX_AES_STS_AUDIO_SIG_PRE_EMPH_SHIFT   (2)
 Audio signal pre- emphasis bit shift. More...
 
#define XI2S_TX_AES_STS_AUDIO_SIG_PRE_EMPH_MASK   (0x7 << XI2S_TX_AES_STS_AUDIO_SIG_PRE_EMPH_SHIFT)
 Audio signal pre-emphasis mask. More...
 
#define XI2S_TX_AES_STS_LOCK_INDICATION_SHIFT   (5)
 lock indication bit shift More...
 
#define XI2S_TX_AES_STS_LOCK_INDICATION_MASK   (1 << XI2S_TX_AES_STS_LOCK_INDICATION_SHIFT)
 Lock indication mask. More...
 
#define XI2S_TX_AES_STS_SAMPLING_FREQ_E_SHIFT   (6)
 Sampling Frequency 0 bit shift. More...
 
#define XI2S_TX_AES_STS_SAMPLING_FREQ_E_MASK   (0x3 << XI2S_TX_AES_STS_SAMPLING_FREQ_E_SHIFT)
 Sampling Frequency 0 mask. More...
 
#define XI2S_TX_AES_STS_CH_MODE_SHIFT   (0)
 Channel mode bit shift. More...
 
#define XI2S_TX_AES_STS_CH_MODE_MASK   (0xF << XI2S_TX_AES_STS_CH_MODE_SHIFT)
 Channel mode mask. More...
 
#define XI2S_TX_AES_STS_USR_BITS_MGMT_SHIFT   (4)
 User Bits Management bit shift. More...
 
#define XI2S_TX_AES_STS_USR_BITS_MGMT_MASK   (0xF << XI2S_TX_AES_STS_USR_BITS_MGMT_SHIFT)
 User Bits Management mask. More...
 
#define XI2S_TX_AES_STS_USEOF_AUX_SMPL_BITS_SHIFT   (0)
 Use of auxiliary sample bits bit shift. More...
 
#define XI2S_TX_AES_STS_USEOF_AUX_SMPL_BITS_MASK   (0x7 << XI2S_TX_AES_STS_USEOF_AUX_SMPL_BITS_SHIFT)
 Use of Auxiliary sample bits mask. More...
 
#define XI2S_TX_AES_STS_SRC_WORD_LENGTH_SHIFT   (3)
 Source word length bit shift. More...
 
#define XI2S_TX_AES_STS_SRC_WORD_LENGTH_MASK   (0x7 << XI2S_TX_AES_STS_SRC_WORD_LENGTH_SHIFT)
 Source word length mask. More...
 
#define XI2S_TX_AES_STS_INDICATE_ALIGN_LEVEL_SHIFT   (6)
 Indication of Alignment level bit shift. More...
 
#define XI2S_TX_AES_STS_INDICATE_ALIGN_LEVEL_MASK   (0x3 << XI2S_TX_AES_STS_INDICATE_ALIGN_LEVEL_SHIFT)
 Indication of Alignment level mask. More...
 
#define XI2S_TX_AES_STS_CH_NUM0_SHIFT   (0)
 Channel Number (0) bit shift. More...
 
#define XI2S_TX_AES_STS_CH_NUM0_MASK   (0x7F << XI2S_TX_AES_STS_CH_NUM0_SHIFT)
 Channel Number (0) mask. More...
 
#define XI2S_TX_AES_STS_MC_CH_MODE_SHIFT   (7)
 Multichannel mode bit shift. More...
 
#define XI2S_TX_AES_STS_MC_CH_MODE_MASK   (1 << XI2S_TX_AES_STS_MC_CH_MODE_SHIFT)
 Multichannel mode mask. More...
 
#define XI2S_TX_AES_STS_CH_NUM1_SHIFT   (0)
 Channel Number (1) bit shift. More...
 
#define XI2S_TX_AES_STS_CH_NUM1_MASK   (0xF << XI2S_TX_AES_STS_CH_NUM1_SHIFT)
 Channel Number (1) mask. More...
 
#define XI2S_TX_AES_STS_MC_CH_MODE_NUM_SHIFT   (4)
 Multichannel mode number bit shift. More...
 
#define XI2S_TX_AES_STS_MC_CH_MODE_NUM_MASK   (0x7 << XI2S_TX_AES_STS_MC_CH_MODE_NUM_SHIFT)
 Multichannel mode number mask. More...
 
#define XI2S_TX_AES_STS_DIGITAL_AUDIO_REF_SIG_SHIFT   (0)
 Digital Reference Audio signal bit shift. More...
 
#define XI2S_TX_AES_STS_DIGITAL_AUDIO_REF_SIG_MASK   (0x3 << XI2S_TX_AES_STS_DIGITAL_AUDIO_REF_SIG_SHIFT)
 Digital Reference Audio signal mask. More...
 
#define XI2S_TX_AES_STS_RSVD_BUT_UNDEF0_SHIFT   (2)
 Reserved but undefined (0) bit shift. More...
 
#define XI2S_TX_AES_STS_RSVD_BUT_UNDEF0_MASK   (1 << XI2S_TX_AES_STS_RSVD_BUT_UNDEF0_SHIFT)
 Reserved but undefined (0) mask. More...
 
#define XI2S_TX_AES_STS_SAMPLING_FREQ_Q_SHIFT   (3)
 Sampling Frequency (1) bit shift. More...
 
#define XI2S_TX_AES_STS_SAMPLING_FREQ_Q_MASK   (0xF << XI2S_TX_AES_STS_SAMPLING_FREQ_Q_SHIFT)
 Sampling Frequency (1) mask. More...
 
#define XI2S_TX_AES_STS_SAMPLING_FREQ_SCALE_FLAG_SHIFT   (7)
 Sampling Frequency scaling flag bit shift. More...
 
#define XI2S_TX_AES_STS_SAMPLING_FREQ_SCALE_FLAG_MASK   (1 << XI2S_TX_AES_STS_SAMPLING_FREQ_SCALE_FLAG_SHIFT)
 Sampling Frequency scaling flag mask. More...
 
#define XI2S_TX_AES_STS_RSVD_BUT_UNDEF1_SHIFT   (0)
 Reserved but undefined (1) bit shift. More...
 
#define XI2S_TX_AES_STS_RSVD_BUT_UNDEF1_MASK   (0xFF << XI2S_TX_AES_STS_RSVD_BUT_UNDEF1_SHIFT)
 Reserved but undefined (1) mask. More...
 
#define XI2S_TX_AES_STS_ALPHANUM_CH_ORG_DATA_OFFSET   (6)
 Alphanumeric channel origin data register(s) offset. More...
 
#define XI2S_TX_AES_STS_ALPHANUM_CH_DEST_DATA_OFFSET   (10)
 Alphanumeric channel destination data bit shift. More...
 
#define XI2S_TX_AES_STS_LOCAL_SAMPLE_ADDRCODE_OFFSET   (14)
 Local sample address code register(s) offset. More...
 
#define XI2S_TX_AES_STS_TIMEOFDAY_SAMPLE_ADDRCODE_OFFSET   (18)
 Time-of-day sample address code register(s) offset. More...
 
#define XI2S_TX_AES_STS_RELIABLE_FLAGS_OFFSET   (22)
 Reliability flags bit shift. More...
 
#define XI2S_TX_AES_STS_CRC_CHAR_OFFSET   (23)
 Cyclic redundancy check character bit shift. More...
 
#define XI2S_TX_LOG_ITEM_BUFFER_SIZE   (256)
 @ name Log Item Buffer Size More...
 

XI2s_Tx_LogEvt

enum  XI2s_Tx_LogEvt {
  XI2S_TX_AES_BLKCMPLT_EVT, XI2S_TX_AES_BLKSYNCERR_EVT, XI2S_TX_AES_CHSTSUPD_EVT, XI2S_TX_AUD_UNDRFLW_EVT,
  XI2S_TX_LOG_EVT_INVALID
}
 These constants specify different types of handlers and is used to differentiate interrupt requests from the I2S Transmitter peripheral. More...
 

Register Map

Register offsets for the XI2S_Transmitter device.

#define XI2S_TX_CORE_VER_OFFSET   0x00
 Core Version Register. More...
 
#define XI2S_TX_CORE_CFG_OFFSET   0x04
 Core Configuration Register. More...
 
#define XI2S_TX_CORE_CTRL_OFFSET   0x08
 Core Control Register. More...
 
#define XI2S_TX_IRQCTRL_OFFSET   0x10
 Interrupt Control Register. More...
 
#define XI2S_TX_IRQSTS_OFFSET   0x14
 Interrupt Status Register. More...
 
#define XI2S_TX_TMR_CTRL_OFFSET   0x20
 I2S Timing Control Register. More...
 
#define XI2S_TX_CH01_OFFSET   0x30
 Audio Channel 0/1 Control Register. More...
 
#define XI2S_TX_CH23_OFFSET   0x34
 Audio Channel 2/3 Control Register. More...
 
#define XI2S_TX_CH45_OFFSET   0x38
 Audio Channel 4/5 Control Register. More...
 
#define XI2S_TX_CH67_OFFSET   0x3C
 Audio Channel 6/7 Control Register. More...
 
#define XI2S_TX_AES_CHSTS0_OFFSET   0x50
 AES Channel Status 0 Register. More...
 
#define XI2S_TX_AES_CHSTS1_OFFSET   0x54
 AES Channel Status 1 Register. More...
 
#define XI2S_TX_AES_CHSTS2_OFFSET   0x58
 AES Channel Status 2 Register. More...
 
#define XI2S_TX_AES_CHSTS3_OFFSET   0x5C
 AES Channel Status 3 Register. More...
 
#define XI2S_TX_AES_CHSTS4_OFFSET   0x60
 AES Channel Status 4 Register. More...
 
#define XI2S_TX_AES_CHSTS5_OFFSET   0x64
 AES Channel Status 5 Register. More...
 

Core Configuration Register masks and shifts

#define XI2S_TX_REG_CFG_MSTR_SHIFT   (0)
 Is I2S Master bit shift. More...
 
#define XI2S_TX_REG_CFG_MSTR_MASK   (1 << XI2S_TX_REG_CFG_MSTR_SHIFT)
 Is I2S Master mask. More...
 
#define XI2S_TX_REG_CFG_NUM_CH_SHIFT   (8)
 Maximum number of channels bit shift. More...
 
#define XI2S_TX_REG_CFG_NUM_CH_MASK   (0xF << XI2S_TX_REG_CFG_NUM_CH_SHIFT)
 Maximum number of channels mask. More...
 
#define XI2S_TX_REG_CFG_DWDTH_SHIFT   (16)
 I2S Data Width bit shift. More...
 
#define XI2S_TX_REG_CFG_DWDTH_MASK   (1 << XI2S_TX_REG_CFG_DWDTH_SHIFT)
 I2S Data Width mask. More...
 

Core Control Register masks and shifts

#define XI2S_TX_REG_CTRL_EN_SHIFT   (0)
 Module Enable bit shift. More...
 
#define XI2S_TX_REG_CTRL_EN_MASK   (1 << XI2S_TX_REG_CTRL_EN_SHIFT)
 Module Enable mask. More...
 
#define XI2S_TX_REG_CTRL_JFE_SHIFT   (1)
 Justification Enable or Disable shift. More...
 
#define XI2S_TX_REG_CTRL_JFE_MASK   (1 << XI2S_TX_REG_CTRL_JFE_SHIFT)
 Justification Enable or Disable mask. More...
 
#define XI2S_TX_REG_CTRL_LORJF_SHIFT   (2)
 Left or Right Justification shift. More...
 
#define XI2S_TX_REG_CTRL_LORJF_MASK   (1 << XI2S_TX_REG_CTRL_LORJF_SHIFT)
 Left or Right Justification mask. More...
 

Interrupt masks and shifts

#define XI2S_TX_INTR_AES_BLKCMPLT_SHIFT   (0)
 AES Block Complete Interrupt bit shift. More...
 
#define XI2S_TX_INTR_AES_BLKCMPLT_MASK   (1 << XI2S_TX_INTR_AES_BLKCMPLT_SHIFT)
 AES Block Complete Interrupt mask. More...
 
#define XI2S_TX_INTR_AES_BLKSYNCERR_SHIFT   (1)
 AES Block Synchronization Error Interrupt bit shift. More...
 
#define XI2S_TX_INTR_AES_BLKSYNCERR_MASK   (1 << XI2S_TX_INTR_AES_BLKSYNCERR_SHIFT)
 AES Block Synchronization Error Interrupt mask. More...
 
#define XI2S_TX_INTR_AES_CHSTSUPD_SHIFT   (2)
 AES Channel Status Updated Interrupt bit shift. More...
 
#define XI2S_TX_INTR_AES_CHSTSUPD_MASK   (1 << XI2S_TX_INTR_AES_CHSTSUPD_SHIFT)
 AES Channel Status Updated Interrupt mask. More...
 
#define XI2S_TX_INTR_AUDUNDRFLW_SHIFT   (3)
 Audio Underflow Detected Interrupt bit shift. More...
 
#define XI2S_TX_INTR_AUDUNDRFLW_MASK   (1 << XI2S_TX_INTR_AUDUNDRFLW_SHIFT)
 Audio Underflow Detected Interrupt mask. More...
 
#define XI2S_TX_GINTR_EN_SHIFT   (31)
 Global Interrupt Enable bit shift. More...
 
#define XI2S_TX_GINTR_EN_MASK   (1 << XI2S_TX_GINTR_EN_SHIFT)
 Global Interrupt Enable mask. More...
 

I2S Timing Control Register masks and shifts

#define XI2S_TX_REG_TMR_SCLKDIV_SHIFT   (0)
 SClk Divider bit shift. More...
 
#define XI2S_TX_REG_TMR_SCLKDIV_MASK   (0xF << XI2S_TX_REG_TMR_SCLKDIV_SHIFT)
 SClk Divider mask. More...
 

Audio Channel Control Register masks and shifts

#define XI2S_TX_REG_CHCTRL_CHMUX_SHIFT   (0)
 Channel MUX bit shift. More...
 
#define XI2S_TX_REG_CHCTRL_CHMUX_MASK   (0x7 << XI2S_TX_REG_CHCTRL_CHMUX_SHIFT)
 Channel MUX mask. More...
 

Register access macro definition

#define XI2s_Tx_In32   Xil_In32
 Input Operations. More...
 
#define XI2s_Tx_Out32   Xil_Out32
 Output Operations. More...
 
#define XI2s_Tx_ReadReg(BaseAddress, RegOffset)   XI2s_Tx_In32((BaseAddress) + ((u32)RegOffset))
 This macro reads a value from a I2S Transmitter register. More...
 
#define XI2s_Tx_WriteReg(BaseAddress, RegOffset, Data)   XI2s_Tx_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))
 This macro writes a value to a I2S Transmitter register. More...
 

Macro Definition Documentation

#define XI2S_TX_AES_CHSTS0_OFFSET   0x50

AES Channel Status 0 Register.

Referenced by XI2s_Tx_ClrAesChStatRegs(), and XI2s_Tx_GetAesChStatus().

#define XI2S_TX_AES_CHSTS1_OFFSET   0x54

AES Channel Status 1 Register.

Referenced by XI2s_Tx_ClrAesChStatRegs().

#define XI2S_TX_AES_CHSTS2_OFFSET   0x58

AES Channel Status 2 Register.

Referenced by XI2s_Tx_ClrAesChStatRegs().

#define XI2S_TX_AES_CHSTS3_OFFSET   0x5C

AES Channel Status 3 Register.

Referenced by XI2s_Tx_ClrAesChStatRegs().

#define XI2S_TX_AES_CHSTS4_OFFSET   0x60

AES Channel Status 4 Register.

Referenced by XI2s_Tx_ClrAesChStatRegs().

#define XI2S_TX_AES_CHSTS5_OFFSET   0x64

AES Channel Status 5 Register.

Referenced by XI2s_Tx_ClrAesChStatRegs().

#define XI2S_TX_AES_STS_ALPHANUM_CH_DEST_DATA_OFFSET   (10)

Alphanumeric channel destination data bit shift.

#define XI2S_TX_AES_STS_ALPHANUM_CH_ORG_DATA_OFFSET   (6)

Alphanumeric channel origin data register(s) offset.

#define XI2S_TX_AES_STS_AUDIO_SIG_PRE_EMPH_MASK   (0x7 << XI2S_TX_AES_STS_AUDIO_SIG_PRE_EMPH_SHIFT)

Audio signal pre-emphasis mask.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_AUDIO_SIG_PRE_EMPH_SHIFT   (2)

Audio signal pre- emphasis bit shift.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_CH_MODE_MASK   (0xF << XI2S_TX_AES_STS_CH_MODE_SHIFT)

Channel mode mask.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_CH_MODE_SHIFT   (0)

Channel mode bit shift.

#define XI2S_TX_AES_STS_CH_NUM0_MASK   (0x7F << XI2S_TX_AES_STS_CH_NUM0_SHIFT)

Channel Number (0) mask.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_CH_NUM0_SHIFT   (0)

Channel Number (0) bit shift.

#define XI2S_TX_AES_STS_CH_NUM1_MASK   (0xF << XI2S_TX_AES_STS_CH_NUM1_SHIFT)

Channel Number (1) mask.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_CH_NUM1_SHIFT   (0)

Channel Number (1) bit shift.

#define XI2S_TX_AES_STS_CRC_CHAR_OFFSET   (23)

Cyclic redundancy check character bit shift.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_DIGITAL_AUDIO_REF_SIG_MASK   (0x3 << XI2S_TX_AES_STS_DIGITAL_AUDIO_REF_SIG_SHIFT)

Digital Reference Audio signal mask.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_DIGITAL_AUDIO_REF_SIG_SHIFT   (0)

Digital Reference Audio signal bit shift.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_INDICATE_ALIGN_LEVEL_MASK   (0x3 << XI2S_TX_AES_STS_INDICATE_ALIGN_LEVEL_SHIFT)

Indication of Alignment level mask.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_INDICATE_ALIGN_LEVEL_SHIFT   (6)

Indication of Alignment level bit shift.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_LINEAR_PCM_ID_MASK   (1 << XI2S_TX_AES_STS_LINEAR_PCM_ID_SHIFT)

Linear PCM Identification mask.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_LINEAR_PCM_ID_SHIFT   (1)

Linear PCM Identification bit shift.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_LOCAL_SAMPLE_ADDRCODE_OFFSET   (14)

Local sample address code register(s) offset.

#define XI2S_TX_AES_STS_LOCK_INDICATION_MASK   (1 << XI2S_TX_AES_STS_LOCK_INDICATION_SHIFT)

Lock indication mask.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_LOCK_INDICATION_SHIFT   (5)

lock indication bit shift

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_MC_CH_MODE_MASK   (1 << XI2S_TX_AES_STS_MC_CH_MODE_SHIFT)

Multichannel mode mask.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_MC_CH_MODE_NUM_MASK   (0x7 << XI2S_TX_AES_STS_MC_CH_MODE_NUM_SHIFT)

Multichannel mode number mask.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_MC_CH_MODE_NUM_SHIFT   (4)

Multichannel mode number bit shift.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_MC_CH_MODE_SHIFT   (7)

Multichannel mode bit shift.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_RELIABLE_FLAGS_OFFSET   (22)

Reliability flags bit shift.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_RSVD_BUT_UNDEF0_MASK   (1 << XI2S_TX_AES_STS_RSVD_BUT_UNDEF0_SHIFT)

Reserved but undefined (0) mask.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_RSVD_BUT_UNDEF0_SHIFT   (2)

Reserved but undefined (0) bit shift.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_RSVD_BUT_UNDEF1_MASK   (0xFF << XI2S_TX_AES_STS_RSVD_BUT_UNDEF1_SHIFT)

Reserved but undefined (1) mask.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_RSVD_BUT_UNDEF1_SHIFT   (0)

Reserved but undefined (1) bit shift.

#define XI2S_TX_AES_STS_SAMPLING_FREQ_E_MASK   (0x3 << XI2S_TX_AES_STS_SAMPLING_FREQ_E_SHIFT)

Sampling Frequency 0 mask.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_SAMPLING_FREQ_E_SHIFT   (6)

Sampling Frequency 0 bit shift.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_SAMPLING_FREQ_Q_MASK   (0xF << XI2S_TX_AES_STS_SAMPLING_FREQ_Q_SHIFT)

Sampling Frequency (1) mask.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_SAMPLING_FREQ_Q_SHIFT   (3)

Sampling Frequency (1) bit shift.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_SAMPLING_FREQ_SCALE_FLAG_MASK   (1 << XI2S_TX_AES_STS_SAMPLING_FREQ_SCALE_FLAG_SHIFT)

Sampling Frequency scaling flag mask.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_SAMPLING_FREQ_SCALE_FLAG_SHIFT   (7)

Sampling Frequency scaling flag bit shift.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_SRC_WORD_LENGTH_MASK   (0x7 << XI2S_TX_AES_STS_SRC_WORD_LENGTH_SHIFT)

Source word length mask.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_SRC_WORD_LENGTH_SHIFT   (3)

Source word length bit shift.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_TIMEOFDAY_SAMPLE_ADDRCODE_OFFSET   (18)

Time-of-day sample address code register(s) offset.

#define XI2S_TX_AES_STS_USE_OF_CH_STS_BLK_MASK   (1 << XI2S_TX_AES_STS_USE_OF_CH_STS_BLK_SHIFT)

Use of Channel Status Block mask.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_USE_OF_CH_STS_BLK_SHIFT   (0)

Use of Channel Status Block bit shift.

#define XI2S_TX_AES_STS_USEOF_AUX_SMPL_BITS_MASK   (0x7 << XI2S_TX_AES_STS_USEOF_AUX_SMPL_BITS_SHIFT)

Use of Auxiliary sample bits mask.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_USEOF_AUX_SMPL_BITS_SHIFT   (0)

Use of auxiliary sample bits bit shift.

#define XI2S_TX_AES_STS_USR_BITS_MGMT_MASK   (0xF << XI2S_TX_AES_STS_USR_BITS_MGMT_SHIFT)

User Bits Management mask.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_AES_STS_USR_BITS_MGMT_SHIFT   (4)

User Bits Management bit shift.

Referenced by XI2s_Tx_ReslveAesChStat().

#define XI2S_TX_CH01_OFFSET   0x30

Audio Channel 0/1 Control Register.

Referenced by XI2s_Tx_SetChMux().

#define XI2S_TX_CH23_OFFSET   0x34

Audio Channel 2/3 Control Register.

#define XI2S_TX_CH45_OFFSET   0x38

Audio Channel 4/5 Control Register.

#define XI2S_TX_CH67_OFFSET   0x3C

Audio Channel 6/7 Control Register.

#define XI2S_TX_CORE_CFG_OFFSET   0x04

Core Configuration Register.

#define XI2S_TX_CORE_CTRL_OFFSET   0x08

Core Control Register.

Referenced by XI2s_Tx_Enable(), XI2s_Tx_Justify(), and XI2s_Tx_JustifyEnable().

#define XI2S_TX_CORE_VER_OFFSET   0x00

Core Version Register.

#define XI2s_Tx_GetMaxChannels (   InstancePtr)
Value:
((XI2s_Tx_ReadReg((InstancePtr)->Config.BaseAddress, (XI2S_TX_CORE_CFG_OFFSET))\
& XI2S_TX_REG_CFG_NUM_CH_MASK) >> XI2S_TX_REG_CFG_NUM_CH_SHIFT)
XI2S_TX_CORE_CFG_OFFSET
#define XI2S_TX_CORE_CFG_OFFSET
Core Configuration Register.
Definition: xi2stx_hw.h:46
XI2S_TX_REG_CFG_NUM_CH_SHIFT
#define XI2S_TX_REG_CFG_NUM_CH_SHIFT
Maximum number of channels bit shift.
Definition: xi2stx_hw.h:75
XI2s_Tx_ReadReg
#define XI2s_Tx_ReadReg(BaseAddress, RegOffset)
This macro reads a value from a I2S Transmitter register.
Definition: xi2stx_hw.h:192
XI2S_TX_REG_CFG_NUM_CH_MASK
#define XI2S_TX_REG_CFG_NUM_CH_MASK
Maximum number of channels mask.
Definition: xi2stx_hw.h:78

This macro reads the maximum number of I2S channels available.

Parameters
InstancePtris a pointer to the XI2s_Tx core instance.
Returns
Maximum number of I2S Channels.
Note
C-style signature: u32 XI2s_Tx_GetMaxChannels(XI2s_Tx *InstancePtr)

Referenced by XI2s_Tx_SelfTest().

#define XI2S_TX_GINTR_EN_MASK   (1 << XI2S_TX_GINTR_EN_SHIFT)

Global Interrupt Enable mask.

Referenced by I2sTxIntrExample().

#define XI2S_TX_GINTR_EN_SHIFT   (31)

Global Interrupt Enable bit shift.

#define XI2s_Tx_In32   Xil_In32

Input Operations.

#define XI2S_TX_INTR_AES_BLKCMPLT_MASK   (1 << XI2S_TX_INTR_AES_BLKCMPLT_SHIFT)

AES Block Complete Interrupt mask.

Referenced by I2sTxIntrExample(), and XI2s_Tx_IntrHandler().

#define XI2S_TX_INTR_AES_BLKCMPLT_SHIFT   (0)

AES Block Complete Interrupt bit shift.

#define XI2S_TX_INTR_AES_BLKSYNCERR_MASK   (1 << XI2S_TX_INTR_AES_BLKSYNCERR_SHIFT)

AES Block Synchronization Error Interrupt mask.

Referenced by XI2s_Tx_IntrHandler().

#define XI2S_TX_INTR_AES_BLKSYNCERR_SHIFT   (1)

AES Block Synchronization Error Interrupt bit shift.

#define XI2S_TX_INTR_AES_CHSTSUPD_MASK   (1 << XI2S_TX_INTR_AES_CHSTSUPD_SHIFT)

AES Channel Status Updated Interrupt mask.

Referenced by XI2s_Tx_IntrHandler().

#define XI2S_TX_INTR_AES_CHSTSUPD_SHIFT   (2)

AES Channel Status Updated Interrupt bit shift.

#define XI2S_TX_INTR_AUDUNDRFLW_MASK   (1 << XI2S_TX_INTR_AUDUNDRFLW_SHIFT)

Audio Underflow Detected Interrupt mask.

Referenced by I2sTxIntrExample(), and XI2s_Tx_IntrHandler().

#define XI2S_TX_INTR_AUDUNDRFLW_SHIFT   (3)

Audio Underflow Detected Interrupt bit shift.

#define XI2S_TX_IRQCTRL_OFFSET   0x10

Interrupt Control Register.

Referenced by XI2s_Tx_IntrDisable(), XI2s_Tx_IntrEnable(), and XI2s_Tx_IntrHandler().

#define XI2S_TX_IRQSTS_OFFSET   0x14

Interrupt Status Register.

Referenced by XI2s_Tx_IntrHandler().

#define XI2s_Tx_IsI2sMaster (   InstancePtr)
Value:
((XI2s_Tx_ReadReg((InstancePtr)->Config.BaseAddress, \
(XI2S_TX_CORE_CFG_OFFSET)) \
& XI2S_TX_REG_CFG_MSTR_MASK) ? TRUE : FALSE)
XI2S_TX_CORE_CFG_OFFSET
#define XI2S_TX_CORE_CFG_OFFSET
Core Configuration Register.
Definition: xi2stx_hw.h:46
XI2S_TX_REG_CFG_MSTR_MASK
#define XI2S_TX_REG_CFG_MSTR_MASK
Is I2S Master mask.
Definition: xi2stx_hw.h:72
XI2s_Tx_ReadReg
#define XI2s_Tx_ReadReg(BaseAddress, RegOffset)
This macro reads a value from a I2S Transmitter register.
Definition: xi2stx_hw.h:192

This macro returns the I2S operating mode.

Parameters
InstancePtris a pointer to the XI2s_Tx core instance.
Returns
  • TRUE : is I2S Master
  • FALSE : is I2S Slave
Note
C-style signature: u8 XI2s_Tx_IsI2sMaster(XI2s_Tx *InstancePtr)

Referenced by XI2s_Tx_SelfTest().

#define XI2S_TX_LOG_ITEM_BUFFER_SIZE   (256)

@ name Log Item Buffer Size

#define XI2s_Tx_Out32   Xil_Out32

Output Operations.

#define XI2s_Tx_ReadReg (   BaseAddress,
  RegOffset 
)    XI2s_Tx_In32((BaseAddress) + ((u32)RegOffset))

This macro reads a value from a I2S Transmitter register.

A 32 bit read is performed. If the component is implemented in a smaller width, only the least significant data is read from the register. The most significant data will be read as 0.

Parameters
BaseAddressis the base address of the I2S Transmitter core instance.
RegOffsetis the register offset of the register (defined at the top of this file).
Returns
The 32-bit value of the register.
Note
C-style signature: u32 XI2S_Tx_ReadReg(u32 BaseAddress, u32 RegOffset)

Referenced by XI2s_Tx_Enable(), XI2s_Tx_GetAesChStatus(), XI2s_Tx_IntrDisable(), XI2s_Tx_IntrEnable(), XI2s_Tx_IntrHandler(), XI2s_Tx_Justify(), and XI2s_Tx_JustifyEnable().

#define XI2S_TX_REG_CFG_DWDTH_MASK   (1 << XI2S_TX_REG_CFG_DWDTH_SHIFT)

I2S Data Width mask.

#define XI2S_TX_REG_CFG_DWDTH_SHIFT   (16)

I2S Data Width bit shift.

#define XI2S_TX_REG_CFG_MSTR_MASK   (1 << XI2S_TX_REG_CFG_MSTR_SHIFT)

Is I2S Master mask.

#define XI2S_TX_REG_CFG_MSTR_SHIFT   (0)

Is I2S Master bit shift.

#define XI2S_TX_REG_CFG_NUM_CH_MASK   (0xF << XI2S_TX_REG_CFG_NUM_CH_SHIFT)

Maximum number of channels mask.

#define XI2S_TX_REG_CFG_NUM_CH_SHIFT   (8)

Maximum number of channels bit shift.

#define XI2S_TX_REG_CHCTRL_CHMUX_MASK   (0x7 << XI2S_TX_REG_CHCTRL_CHMUX_SHIFT)

Channel MUX mask.

#define XI2S_TX_REG_CHCTRL_CHMUX_SHIFT   (0)

Channel MUX bit shift.

#define XI2S_TX_REG_CTRL_EN_MASK   (1 << XI2S_TX_REG_CTRL_EN_SHIFT)

Module Enable mask.

Referenced by XI2s_Tx_Enable().

#define XI2S_TX_REG_CTRL_EN_SHIFT   (0)

Module Enable bit shift.

#define XI2S_TX_REG_CTRL_JFE_MASK   (1 << XI2S_TX_REG_CTRL_JFE_SHIFT)

Justification Enable or Disable mask.

Referenced by XI2s_Tx_JustifyEnable().

#define XI2S_TX_REG_CTRL_JFE_SHIFT   (1)

Justification Enable or Disable shift.

#define XI2S_TX_REG_CTRL_LORJF_MASK   (1 << XI2S_TX_REG_CTRL_LORJF_SHIFT)

Left or Right Justification mask.

Referenced by XI2s_Tx_Justify().

#define XI2S_TX_REG_CTRL_LORJF_SHIFT   (2)

Left or Right Justification shift.

#define XI2S_TX_REG_TMR_SCLKDIV_MASK   (0xF << XI2S_TX_REG_TMR_SCLKDIV_SHIFT)

SClk Divider mask.

#define XI2S_TX_REG_TMR_SCLKDIV_SHIFT   (0)

SClk Divider bit shift.

#define XI2S_TX_TMR_CTRL_OFFSET   0x20

I2S Timing Control Register.

Referenced by XI2s_Tx_SetSclkOutDiv().

#define XI2s_Tx_WriteReg (   BaseAddress,
  RegOffset,
  Data 
)    XI2s_Tx_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))

This macro writes a value to a I2S Transmitter register.

A 32 bit write is performed. If the component is implemented in a smaller width, only the least significant data is written.

Parameters
BaseAddressis the base address of the I2S Transmitter core instance.
RegOffsetis the register offset of the register (defined at the top of this file) to be written.
Datais the 32-bit value to write into the register.
Returns
None.
Note
C-style signature: void XI2S_Tx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)

Referenced by XI2s_Tx_ClrAesChStatRegs(), XI2s_Tx_Enable(), XI2s_Tx_IntrDisable(), XI2s_Tx_IntrEnable(), XI2s_Tx_Justify(), XI2s_Tx_JustifyEnable(), XI2s_Tx_SetChMux(), and XI2s_Tx_SetSclkOutDiv().

Enumeration Type Documentation

enum XI2s_Tx_ChannelId

These constants specify different channel ID's.

Enumerator
XI2S_TX_CHID0 

Channel 0.

XI2S_TX_CHID1 

Channel 1.

XI2S_TX_CHID2 

Channel 2.

XI2S_TX_CHID3 

Channel 3.

XI2S_TX_NUM_CHANNELS 

Number of Channel ID's.

enum XI2s_Tx_HandlerType

these constants specify different types of handlers and is used to differentiate interrupt requests from the I2s Transmitter peripheral.

Enumerator
XI2S_TX_HANDLER_AES_BLKCMPLT 

AES Block Complete Handler.

XI2S_TX_HANDLER_AES_BLKSYNCERR 

AES Block Sync Error Handler.

XI2S_TX_HANDLER_AES_CHSTSUPD 

AES Channel Status Updated Handler.

XI2S_TX_HANDLER_AUD_UNDRFLW 

Audio Underflow Detected Handler.

XI2S_TX_NUM_HANDLERS 

Number of handler types.

enum XI2s_Tx_LogEvt

These constants specify different types of handlers and is used to differentiate interrupt requests from the I2S Transmitter peripheral.

Enumerator
XI2S_TX_AES_BLKCMPLT_EVT 

AES Block Complete Event.

XI2S_TX_AES_BLKSYNCERR_EVT 

AES Block Sync Error Event.

XI2S_TX_AES_CHSTSUPD_EVT 

AES Channel Status Updated Event.

XI2S_TX_AUD_UNDRFLW_EVT 

Audio Underflow Detected Event.

XI2S_TX_LOG_EVT_INVALID 

Invalid Log Event.

Function Documentation

int XI2s_Tx_CfgInitialize ( XI2s_Tx *  InstancePtr,
XI2stx_Config *  CfgPtr,
UINTPTR  EffectiveAddr 
)

This function initializes the I2S Transmitter.

This function must be called prior to using the core. Initialization of the I2S Transmitter includes setting up the instance data, and ensuring the hardware is in a quiescent state.

Parameters
InstancePtris a pointer to the I2s Transmitter instance.
CfgPtrpoints to the configuration structure associated with the I2s Transmitter.
EffectiveAddris the base address of the device. If address translation is being used, then this parameter must reflect the virtual base address. Otherwise, the physical address should be used.
Returns
  • XST_SUCCESS : if successful.
  • XST_FAILURE : otherwise.
Note
None.

References XI2stx_Config::BaseAddress, XI2s_Tx::Config, XI2s_Tx::IsReady, XI2s_Tx_Enable(), and XI2s_Tx_SelfTest().

Referenced by I2sSelfTestExample(), and I2sTxIntrExample().

void XI2s_Tx_ClrAesChStatRegs ( XI2s_Tx *  InstancePtr)

This function clears the captured AES Channel Status bits.

This will clear all the 6 channel status registers.

Parameters
InstancePtris a pointer to the XI2s_Tx core instance.
Returns
None.

References XI2S_TX_AES_CHSTS0_OFFSET, XI2S_TX_AES_CHSTS1_OFFSET, XI2S_TX_AES_CHSTS2_OFFSET, XI2S_TX_AES_CHSTS3_OFFSET, XI2S_TX_AES_CHSTS4_OFFSET, XI2S_TX_AES_CHSTS5_OFFSET, and XI2s_Tx_WriteReg.

void XI2s_Tx_Enable ( XI2s_Tx *  InstancePtr,
u8  Enable 
)

This function enables/disables the I2s Transmitter.

Parameters
InstancePtris a pointer to the I2s Transmitter instance.
Enablespecifies TRUE/FALSE value to either enable or disable the I2s Transmitter.
Returns
None.

References XI2stx_Config::BaseAddress, XI2s_Tx::Config, XI2s_Tx::IsStarted, XI2S_TX_CORE_CTRL_OFFSET, XI2s_Tx_ReadReg, XI2S_TX_REG_CTRL_EN_MASK, and XI2s_Tx_WriteReg.

Referenced by I2sTxIntrExample(), and XI2s_Tx_CfgInitialize().

void XI2s_Tx_GetAesChStatus ( XI2s_Tx *  InstancePtr,
u8 *  AesChStatusBuf 
)

This function gets the captured AES Channel Status bits.

Parameters
InstancePtris a pointer to the I2s Transmitter instance.
AesChStatusBufis a pointer to a buffer that is used for writing the AES Channel Status bits, this needs to be allocated by user application
Returns
None.

References XI2stx_Config::BaseAddress, XI2s_Tx::Config, XI2S_TX_AES_CHSTS0_OFFSET, and XI2s_Tx_ReadReg.

void XI2s_Tx_IntrDisable ( XI2s_Tx *  InstancePtr,
u32  Mask 
)

This function disables the specified interrupt of the I2s Transmitter.

Parameters
InstancePtris a pointer to the I2s Transmitter instance.
Maskis a bit mask of the interrupts to be disabled.
Returns
None.
See Also
XI2stx_HW for the available interrupt masks.

References XI2stx_Config::BaseAddress, XI2s_Tx::Config, XI2S_TX_IRQCTRL_OFFSET, XI2s_Tx_ReadReg, and XI2s_Tx_WriteReg.

void XI2s_Tx_IntrEnable ( XI2s_Tx *  InstancePtr,
u32  Mask 
)

This function enables the specified interrupt of the I2s Transmitter.

Parameters
InstancePtris a pointer to the I2s Transmitter instance.
Maskis a bit mask of the interrupts to be enabled.
Returns
None.
See Also
XI2stx_hw.h for the available interrupt masks.

References XI2stx_Config::BaseAddress, XI2s_Tx::Config, XI2S_TX_IRQCTRL_OFFSET, XI2s_Tx_ReadReg, and XI2s_Tx_WriteReg.

Referenced by I2sTxIntrExample().

void XI2s_Tx_IntrHandler ( void *  InstancePtr)

This function is the interrupt handler for the I2S Transmitter driver.

This handler reads the pending interrupt from the I2S Transmitter peripheral, determines the source of the interrupts, clears the interrupts and calls callbacks accordingly.

Parameters
InstancePtris a pointer to the XI2s_Tx instance.
Returns
None.
Note
None.

References XI2s_Tx::AesBlkCmpltHandler, XI2s_Tx::AesBlkSyncErrHandler, XI2s_Tx::AudUndrflwHandler, XI2stx_Config::BaseAddress, XI2s_Tx::Config, XI2s_Tx::IsReady, XI2S_TX_AES_BLKCMPLT_EVT, XI2S_TX_AES_BLKSYNCERR_EVT, XI2S_TX_AES_CHSTSUPD_EVT, XI2S_TX_AUD_UNDRFLW_EVT, XI2S_TX_INTR_AES_BLKCMPLT_MASK, XI2S_TX_INTR_AES_BLKSYNCERR_MASK, XI2S_TX_INTR_AES_CHSTSUPD_MASK, XI2S_TX_INTR_AUDUNDRFLW_MASK, XI2S_TX_IRQCTRL_OFFSET, XI2S_TX_IRQSTS_OFFSET, XI2s_Tx_LogWrite(), and XI2s_Tx_ReadReg.

Referenced by I2sTxIntrExample().

void XI2s_Tx_Justify ( XI2s_Tx *  InstancePtr,
XI2s_Tx_Justification  Justify 
)

This function is to enable right/left justification.

Parameters
InstancePtris a pointer to the XI2s Transmitter instance.
Justifyis a enum to select the left or right justfication.
  • XI2S_TX_JUSTIFY_LEFT : Left justication
  • XI2S_TX_JUSTIFY_RIGHT : Right justification
Returns
None.

References XI2stx_Config::BaseAddress, XI2s_Tx::Config, XI2S_TX_CORE_CTRL_OFFSET, XI2s_Tx_ReadReg, XI2S_TX_REG_CTRL_LORJF_MASK, and XI2s_Tx_WriteReg.

void XI2s_Tx_JustifyEnable ( XI2s_Tx *  InstancePtr,
u8  Enable 
)

This function enables/disables the justification.

Parameters
InstancePtris a pointer to the XI2s Transmitter instance.
Enablespecifies TRUE/FALSE value to either enable or disable the justification.
Returns
None.

References XI2stx_Config::BaseAddress, XI2s_Tx::Config, XI2S_TX_CORE_CTRL_OFFSET, XI2s_Tx_ReadReg, XI2S_TX_REG_CTRL_JFE_MASK, and XI2s_Tx_WriteReg.

void XI2s_Tx_LogDisplay ( XI2s_Tx *  InstancePtr)

This function prints the contents of the logging buffer.

Parameters
InstancePtris a pointer to the XI2s_Tx instance.
Returns
None.
Note
None.

References XI2stx_Config::BaseAddress, XI2s_Tx::Config, XI2stx_Config::DeviceId, XI2s_Tx_LogItem::Event, XI2S_TX_AES_BLKCMPLT_EVT, XI2S_TX_AES_BLKSYNCERR_EVT, XI2S_TX_AES_CHSTSUPD_EVT, XI2S_TX_AUD_UNDRFLW_EVT, XI2S_TX_LOG_EVT_INVALID, and XI2s_Tx_LogRead().

XI2s_Tx_LogItem* XI2s_Tx_LogRead ( XI2s_Tx *  InstancePtr)

This function returns the next item in the logging buffer.

Parameters
InstancePtris a pointer to the XI2s_Tx instance.
Returns
When the buffer is filled, the next log item is returned. When the buffer is empty, NULL is returned.
Note
None.

References XI2s_Tx_Log::Head, XI2s_Tx_Log::Items, XI2s_Tx::Log, and XI2s_Tx_Log::Tail.

Referenced by XI2s_Tx_LogDisplay().

void XI2s_Tx_LogReset ( XI2s_Tx *  InstancePtr)

This function clears the contents of the logging buffer.

Parameters
InstancePtris a pointer to the XI2s_Tx instance.
Returns
None.
Note
None.

References XI2s_Tx_Log::Head, XI2s_Tx_Log::IsEnabled, XI2s_Tx::Log, and XI2s_Tx_Log::Tail.

void XI2s_Tx_LogWrite ( XI2s_Tx *  InstancePtr,
XI2s_Tx_LogEvt  Event,
u8  Data 
)

This function writes I2S Transmitter logs into the buffer.

Parameters
InstancePtris a pointer to the XI2s_Tx instance.
Eventis the log event type.
Datais the log data.
Returns
None.
Note
Log write can be done only if the log is enabled.

References XI2s_Tx_LogItem::Data, XI2s_Tx_LogItem::Event, XI2s_Tx_Log::Head, XI2s_Tx_Log::IsEnabled, XI2s_Tx_Log::Items, XI2s_Tx::Log, XI2s_Tx_Log::Tail, and XI2S_TX_LOG_EVT_INVALID.

Referenced by XI2s_Tx_IntrHandler().

XI2stx_Config* XI2s_Tx_LookupConfig ( u16  DeviceId)

This function returns a reference to an XI2stx_Config structure based on the core id, DeviceId.

The return value will refer to an entry in the device configuration table defined in the xi2stx_g.c file.

Parameters
DeviceIdis the unique core ID of the I2S Transmitter core for the lookup operation.
Returns
returns a reference to a config record in the configuration table corresponding to DeviceId, or NULL if no match is found.
Note
None.

Referenced by I2sSelfTestExample(), and I2sTxIntrExample().

void XI2s_Tx_ReslveAesChStat ( u8  I2stx_SrcBuf[])

This function reads the array I2stx_SrcBuf which has the values of all the I2S Transmitter AES status registers, extracts the required bits and prints them.

Before calling this API, Call API XI2s_Tx_GetAesChStatus.

Parameters
I2stx_SrcBufis an array that contains the values of all the the AES Status registers.

< use of channel status block

< linear PCM identification

< audio signal Pre-emphasis

< lock indication

< sampling frequency

< channel mode

< user bits management

< use of auxiliary sample bits

< source word length

< indication of alignment level

< channel mode

< Channel number 0

< Channel number 1

< multi channel1 mode number

< digital audio reference signal

< reserved but undefined

< sampling frequency

< sampling frequency scaling flag

< reserved but undefined

< Alphanumeric channel origin data

< Alphanumeric channel destination data

< Local sample address code

< Time-of-day sample address code

< Reliability flags

< Cyclic redundancy check character

References XI2S_TX_AES_STS_AUDIO_SIG_PRE_EMPH_MASK, XI2S_TX_AES_STS_AUDIO_SIG_PRE_EMPH_SHIFT, XI2S_TX_AES_STS_CH_MODE_MASK, XI2S_TX_AES_STS_CH_NUM0_MASK, XI2S_TX_AES_STS_CH_NUM1_MASK, XI2S_TX_AES_STS_CRC_CHAR_OFFSET, XI2S_TX_AES_STS_DIGITAL_AUDIO_REF_SIG_MASK, XI2S_TX_AES_STS_DIGITAL_AUDIO_REF_SIG_SHIFT, XI2S_TX_AES_STS_INDICATE_ALIGN_LEVEL_MASK, XI2S_TX_AES_STS_INDICATE_ALIGN_LEVEL_SHIFT, XI2S_TX_AES_STS_LINEAR_PCM_ID_MASK, XI2S_TX_AES_STS_LINEAR_PCM_ID_SHIFT, XI2S_TX_AES_STS_LOCK_INDICATION_MASK, XI2S_TX_AES_STS_LOCK_INDICATION_SHIFT, XI2S_TX_AES_STS_MC_CH_MODE_MASK, XI2S_TX_AES_STS_MC_CH_MODE_NUM_MASK, XI2S_TX_AES_STS_MC_CH_MODE_NUM_SHIFT, XI2S_TX_AES_STS_MC_CH_MODE_SHIFT, XI2S_TX_AES_STS_RELIABLE_FLAGS_OFFSET, XI2S_TX_AES_STS_RSVD_BUT_UNDEF0_MASK, XI2S_TX_AES_STS_RSVD_BUT_UNDEF0_SHIFT, XI2S_TX_AES_STS_RSVD_BUT_UNDEF1_MASK, XI2S_TX_AES_STS_SAMPLING_FREQ_E_MASK, XI2S_TX_AES_STS_SAMPLING_FREQ_E_SHIFT, XI2S_TX_AES_STS_SAMPLING_FREQ_Q_MASK, XI2S_TX_AES_STS_SAMPLING_FREQ_Q_SHIFT, XI2S_TX_AES_STS_SAMPLING_FREQ_SCALE_FLAG_MASK, XI2S_TX_AES_STS_SAMPLING_FREQ_SCALE_FLAG_SHIFT, XI2S_TX_AES_STS_SRC_WORD_LENGTH_MASK, XI2S_TX_AES_STS_SRC_WORD_LENGTH_SHIFT, XI2S_TX_AES_STS_USE_OF_CH_STS_BLK_MASK, XI2S_TX_AES_STS_USEOF_AUX_SMPL_BITS_MASK, XI2S_TX_AES_STS_USR_BITS_MGMT_MASK, and XI2S_TX_AES_STS_USR_BITS_MGMT_SHIFT.

int XI2s_Tx_SelfTest ( XI2s_Tx *  InstancePtr)

Runs a self-test on the driver/device.

The self-test is reads the version register, configuration registers and verifies the values

Parameters
InstancePtris a pointer to the XI2s_Tx instance.
Returns
  • XST_SUCCESS if successful i.e. if the self test passes.
  • XST_FAILURE if unsuccessful i.e. if the self test fails
Note
None.

References XI2s_Tx_GetMaxChannels, and XI2s_Tx_IsI2sMaster.

Referenced by I2sSelfTestExample(), I2sTxIntrExample(), and XI2s_Tx_CfgInitialize().

int XI2s_Tx_SetChMux ( XI2s_Tx *  InstancePtr,
XI2s_Tx_ChannelId  ChID,
XI2s_Tx_ChMuxInput  InputSource 
)

This function sets the input source for the specified I2s channel.

Parameters
InstancePtris a pointer to the I2s Transmitter instance.
ChIDspecifies the I2s channel
InputSourcespecifies the input source
Returns
  • XST_SUCCESS : if successful.
  • XST_FAILURE : if the I2s channel is invalid.

References XI2stx_Config::BaseAddress, XI2s_Tx::Config, XI2S_TX_CH01_OFFSET, XI2S_TX_CHMUX_AXIS_01, XI2S_TX_CHMUX_AXIS_23, XI2S_TX_CHMUX_AXIS_45, XI2S_TX_CHMUX_AXIS_67, XI2S_TX_CHMUX_WAVEGEN, XI2S_TX_NUM_CHANNELS, and XI2s_Tx_WriteReg.

Referenced by I2sTxIntrExample().

int XI2s_Tx_SetHandler ( XI2s_Tx *  InstancePtr,
XI2s_Tx_HandlerType  HandlerType,
XI2s_Tx_Callback  FuncPtr,
void *  CallbackRef 
)

This function installs an asynchronous callback function for the given HandlerType: 

HandlerType                              Callback Function
--------------------------------         -------------------------
(XI2S_TX_HANDLER_AES_BLKCMPLT)            AesBlkCmpltHandler
(XI2S_TX_HANDLER_AES_BLKSYNCERR)          AesBlkSyncErrHandler
(XI2S_TX_HANDLER_AES_CHSTSUPD)            AesChStsUpdHandler
(XI2S_TX_HANDLER_AUD_UNDRFLW)             AudUndrflwHandler
Parameters
InstancePtris a pointer to the XI2s_Tx core instance.
HandlerTypespecifies the type of handler.
FuncPtris a pointer to the callback function.
CallbackRefis a reference pointer passed on actual calling of the callback function.
Returns
  • XST_SUCCESS if callback function installed successfully.
  • XST_INVALID_PARAM when HandlerType is invalid.
Note
Invoking this function for a handler that already has been installed replaces it with the new handler.

References XI2s_Tx::AesBlkCmpltHandler, XI2s_Tx::AesBlkSyncErrHandler, XI2s_Tx::AudUndrflwHandler, XI2S_TX_HANDLER_AES_BLKCMPLT, XI2S_TX_HANDLER_AES_BLKSYNCERR, XI2S_TX_HANDLER_AES_CHSTSUPD, XI2S_TX_HANDLER_AUD_UNDRFLW, and XI2S_TX_NUM_HANDLERS.

Referenced by I2sTxIntrExample().

u32 XI2s_Tx_SetSclkOutDiv ( XI2s_Tx *  InstancePtr,
u32  MClk,
u32  Fs 
)

This function calculates the SCLK Output divider value of the I2S timing generator.

Parameters
InstancePtris a pointer to the I2s Transmitter instance.
MClkis the frequency of the MClk.
Fsis the sampling frequency of the system. Divider value for the SCLK generation, MCLK/SCLK = SCLKOUT_DIV x 2 i.e. MCLK = 384xFs, SCLK = 48xFs (2x24bits) -> SCLKOUT_DIV = MCLK/SCLK/2 = 4 Valid values are 1 through 15.
Returns
- XST_FAILURE if SCLK Output divider is not calculated to be a positive integer.
  • XST_SUCCESS, otherwise.

References XI2stx_Config::BaseAddress, XI2s_Tx::Config, XI2stx_Config::DWidth, XI2S_TX_TMR_CTRL_OFFSET, and XI2s_Tx_WriteReg.

Referenced by I2sTxIntrExample().