Data Structures
struct	XDp_lt_fallback_table
	This typedef contains the Displayport link training configuration details. More...

struct	XDp_Config
	This typedef contains configuration information for the DisplayPort core. More...

struct	XDp_TxSinkConfig
	This typedef contains configuration information about the RX device. More...

struct	XDp_TxLinkConfig
	This typedef contains configuration information about the main link settings. More...

struct	XDp_TxLttprConfig
	This typedef contains configuration information about the main link settings. More...

struct	XDp_MainStreamAttributes
	This typedef contains the main stream attributes which determine how the video will be displayed. More...

struct	XDp_TxVscExtPacket
	This typedef contains the VSC extended packet information. More...

struct	XDp_TxMstStream
	This typedef describes a stream when the driver is running in multi-stream transport (MST) mode. More...

struct	XDp_TxBoardChar
	This typedef describes some board characteristics information that affects link training. More...

struct	XDp_TxTopologyNode
	This typedef describes a downstream DisplayPort device when the driver is running in multi-stream transport (MST) mode. More...

struct	XDp_TxTopology
	This typedef describes a the entire topology of connected downstream DisplayPort devices (from the DisplayPort TX) when the driver is operating in multi-stream transport (MST) mode. More...

struct	XDp_TxAudioInfoFrame
	This typedef describes Audio InfoFrame packet. More...

struct	XDp_SbMsgLinkAddressReplyPortDetail
	This typedef describes a port that is connected to a DisplayPort branch device. More...

struct	XDp_SbMsgLinkAddressReplyDeviceInfo
	This typedef describes a DisplayPort branch device. More...

struct	XDp_RxLinkConfig
	This typedef contains configuration information about the main link settings. More...

struct	XDp_RxIicMapEntry
	This typedef represents one I2C map entry for a device. More...

struct	XDp_RxDpcdMap
	This typedef represents the DPCD address map for a device. More...

struct	XDp_RxPort
	This typedef contains information on the directly connected ports to the RX branch. More...

struct	XDp_RxTopology
	This typedef contains topology information on directly connected sinks and of the RX branch itself. More...

struct	XDp_Tx
	The XDp driver instance data representing the TX mode of operation. More...

struct	XDp_Rx
	The XDp driver instance data representing the RX mode of operation. More...

struct	XDp
	The XDp instance data. More...

Macros
#define	XDp_GetCoreType(InstancePtr)
	This is function determines whether the DisplayPort core, represented by the XDp structure pointed to, is a transmitter (TX) or a receiver (RX). More...

#define	XDp_TxCfgSetRGB(InstancePtr, Stream)
	The following functions set the color encoding scheme for a given stream. More...

#define	XDP_RX_NUM_I2C_ENTRIES_PER_PORT 3
	The number of I2C user- defined entries in the I2C map of each port. More...

#define	XDP_GUID_NBYTES 16
	The number of bytes for the global unique ID. More...

#define	XDP_MAX_NPORTS 16
	The maximum number of ports connected to a DisplayPort device. More...

#define	XDp_ReadReg(BaseAddress, RegOffset) XDp_In32((BaseAddress) + (RegOffset))
	This is a low-level function that reads from the specified register. More...

#define	XDp_WriteReg(BaseAddress, RegOffset, Data) XDp_Out32((BaseAddress) + (RegOffset), (Data))
	This is a low-level function that writes to the specified register. More...

Typedefs
typedef void(*	XDp_TimerHandler )(void *InstancePtr, u32 MicroSeconds)
	Callback type which represents a custom timer wait handler. More...

typedef void(*	XDp_IntrHandler )(void *InstancePtr)
	Callback type which represents the handler for interrupts. More...

Enumerations
enum	XDp_CoreType
	This typedef enumerates the RX and TX modes of operation for the DisplayPort core. More...

enum	XDp_DynamicRange
	This typedef enumerates the dynamic ranges available to the DisplayPort core. More...

enum	Dp_Rx_HandlerType
	This typedef enumerates the handlers for the the DisplayPort Receiver. More...

enum	XDp_Tx_HandlerType
	This typedef enumerates the handlers for the the DisplayPort Transmitter. More...

enum	XDp_Tx_LttprMode
	This typedef enumerates the mode of LTTPR. More...

enum	XDp_Tx_LttprCount
	This typedef enumerates the LTTPR count. More...

enum	XDp_lt_lane_count
	This typedef enumerates the Lane count. More...

enum	XDp_lt_link_rate
	This typedef enumerates the Link Rates. More...

Functions
void	XDp_CfgInitialize (XDp InstancePtr, XDp_Config ConfigPtr, UINTPTR EffectiveAddr)
	This function retrieves the configuration for this DisplayPort instance and fills in the InstancePtr->Config structure. More...

u32	XDp_Initialize (XDp *InstancePtr)
	This function prepares the DisplayPort core for use depending on whether the core is operating in TX or RX mode. More...

void	XDp_SetUserTimerHandler (XDp InstancePtr, XDp_TimerHandler CallbackFunc, void CallbackRef)
	This function installs a custom delay/sleep function to be used by the XDp driver. More...

void	XDp_WaitUs (XDp *InstancePtr, u32 MicroSeconds)
	This function is the delay/sleep function for the XDp driver. More...

u8	XDp_IsLinkRateValid (XDp *InstancePtr, u8 LinkRate)
	This function checks the validity of the link rate. More...

u8	XDp_IsLaneCountValid (XDp *InstancePtr, u8 LaneCount)
	This function checks the validity of the lane count. More...

XDp_Config *	XDp_LookupConfig (u16 DeviceId)
	This function looks for the device configuration based on the unique device ID. More...

void	XDp_InterruptHandler (XDp *InstancePtr)
	This function is the interrupt handler for the XDp driver. More...

u32	XDp_SelfTest (XDp *InstancePtr)
	This function runs a self-test on the XDp driver/device depending on whether the core is operating in TX or RX mode. More...

Variables
u8	GuidTable [16][XDP_GUID_NBYTES]
	This table contains a list of global unique identifiers (GUIDs) that will be issued when exploring the topology using the algorithm in the XDp_TxFindAccessibleDpDevices function. More...

XDp_Config	XDp_ConfigTable [XPAR_XDP_NUM_INSTANCES]
	A table of configuration structures containing the configuration information for each DisplayPort TX core in the system. More...

Protocol Selection definitions : DP 1.1, DP 1.2, DP 1.4, DP 2.1.
#define	XDP_PROTOCOL_DP_1_1 0

#define	XDP_PROTOCOL_DP_1_2 1

#define	XDP_PROTOCOL_DP_1_4 2

#define	XDP_PROTOCOL_DP_2_1 3

#define	XDP_TX_TRAINING_MODE_DP14 0x01

#define	XDP_TX_TRAINING_MODE_DP21 0x02

DP generic definitions: Link bandwith and lane count.
#define	XDP_LINK_BW_SET_162GBPS 0x06
	1.62 Gbps link rate. More...

#define	XDP_LINK_BW_SET_270GBPS 0x0A
	2.70 Gbps link rate. More...

#define	XDP_LINK_BW_SET_540GBPS 0x14
	5.40 Gbps link rate. More...

#define	XDP_LINK_BW_SET_810GBPS 0x1E
	8.10 Gbps link rate. More...

#define	XDP_LINK_BW_SET_UHBR10 0x01
	10Gbps link rate. More...

#define	XDP_LINK_BW_SET_UHBR20 0x02
	20Gbps link rate. More...

#define	XDP_TX_LINK_BW_SET_SW_UHBR10 0x20
	10Gbps link rate. More...

#define	XDP_TX_LINK_BW_SET_SW_UHBR20 0x24
	20Gbps link rate. More...

#define	XDP_TX_LINK_BW_SET_SW_UHBR135 0x22
	13.5Gbps link rate. More...

#define	XDP_LINK_BW_SET_UHBR135 0x04
	13.5Gbps link rate. More...

#define	XDP_LANE_COUNT_SET_1 0x01
	Lane count of 1. More...

#define	XDP_LANE_COUNT_SET_2 0x02
	Lane count of 2. More...

#define	XDP_LANE_COUNT_SET_4 0x04
	Lane count of 4. More...

DP generic definitions: Bits per color components.
#define	XDP_MAIN_STREAMX_MISC0_BDC_MASK 0x000000E0
	Bit depth per color component (BDC). More...

#define	XDP_MAIN_STREAMX_MISC0_BDC_SHIFT 5
	Shift bits for BDC. More...

#define	XDP_MAIN_STREAMX_MISC0_BDC_6BPC 0x0
	6 bits per component. More...

#define	XDP_MAIN_STREAMX_MISC0_BDC_8BPC 0x1
	8 bits per component. More...

#define	XDP_MAIN_STREAMX_MISC0_BDC_10BPC 0x2
	10 bits per component. More...

#define	XDP_MAIN_STREAMX_MISC0_BDC_12BPC 0x3
	12 bits per component. More...

#define	XDP_MAIN_STREAMX_MISC0_BDC_16BPC 0x4
	16 bits per component. More...

DP generic definitions: Miscellaneous components; color format.
#define	XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK 0x00000006
	Component format. More...

#define	XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT 1
	Shift bits for component format. More...

#define	XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB 0x0
	Stream's component format is RGB. More...

#define	XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422 0x1
	Stream's component format is YcbCr 4:2:2. More...

#define	XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444 0x2
	Stream's component format is YcbCr 4:4:4. More...

DisplayPort Configuration Data: Receiver capability field.
Address mapping for the DisplayPort Configuration Data (DPCD) of the downstream device.
#define	XDP_DPCD_REV 0x00000

#define	XDP_DPCD_MAX_LINK_RATE 0x00001

#define	XDP_EDID_DPCD_MAX_LINK_RATE 0x02201

#define	XDP_EDID_DPCD_MAINLINKCHANNELCODING 0x02206

#define	XDP_DPCD_FEATURE_ENUMERATION_LIST 0x02210

#define	XDP_DPCD_MAX_LANE_COUNT 0x00002

#define	XDP_DPCD_MAX_DOWNSPREAD 0x00003

#define	XDP_DPCD_NORP_PWR_V_CAP 0x00004

#define	XDP_DPCD_DOWNSP_PRESENT 0x00005

#define	XDP_DPCD_ML_CH_CODING_CAP 0x00006

#define	XDP_DPCD_DOWNSP_COUNT_MSA_OUI 0x00007

#define	XDP_DPCD_RX_PORT0_CAP_0 0x00008

#define	XDP_DPCD_RX_PORT0_CAP_1 0x00009

#define	XDP_DPCD_RX_PORT1_CAP_0 0x0000A

#define	XDP_DPCD_RX_PORT1_CAP_1 0x0000B

#define	XDP_DPCD_I2C_SPEED_CTL_CAP 0x0000C

#define	XDP_DPCD_EDP_CFG_CAP 0x0000D

#define	XDP_DPCD_TRAIN_AUX_RD_INTERVAL 0x0000E

#define	XDP_DPCD_ADAPTER_CAP 0x0000F

#define	XDP_DPCD_MSTM_CAP 0x00021

#define	XDP_DPCD_NUM_AUDIO_EPS 0x00022

#define	XDP_DPCD_AV_GRANULARITY 0x00023

#define	XDP_DPCD_AUD_DEC_LAT_7_0 0x00024

#define	XDP_DPCD_AUD_DEC_LAT_15_8 0x00025

#define	XDP_DPCD_AUD_PP_LAT_7_0 0x00026

#define	XDP_DPCD_AUD_PP_LAT_15_8 0x00027

#define	XDP_DPCD_VID_INTER_LAT 0x00028

#define	XDP_DPCD_VID_PROG_LAT 0x00029

#define	XDP_DPCD_REP_LAT 0x0002A

#define	XDP_DPCD_AUD_DEL_INS_7_0 0x0002B

#define	XDP_DPCD_AUD_DEL_INS_15_8 0x0002C

#define	XDP_DPCD_AUD_DEL_INS_23_16 0x0002D

#define	XDP_DPCD_GUID 0x00030

#define	XDP_DPCD_RX_GTC_VALUE_7_0 0x00054

#define	XDP_DPCD_RX_GTC_VALUE_15_8 0x00055

#define	XDP_DPCD_RX_GTC_VALUE_23_16 0x00056

#define	XDP_DPCD_RX_GTC_VALUE_31_24 0x00057

#define	XDP_DPCD_RX_GTC_MSTR_REQ 0x00058

#define	XDP_DPCD_RX_GTC_FREQ_LOCK_DONE 0x00059

#define	XDP_DPCD_DOWNSP_0_CAP 0x00080

#define	XDP_DPCD_DOWNSP_1_CAP 0x00081

#define	XDP_DPCD_DOWNSP_2_CAP 0x00082

#define	XDP_DPCD_DOWNSP_3_CAP 0x00083

#define	XDP_DPCD_DOWNSP_0_DET_CAP 0x00080

#define	XDP_DPCD_DOWNSP_1_DET_CAP 0x00084

#define	XDP_DPCD_DOWNSP_2_DET_CAP 0x00088

#define	XDP_DPCD_DOWNSP_3_DET_CAP 0x0008C

DisplayPort Configuration Data: Link configuration field.
#define	XDP_DPCD_LINK_BW_SET 0x00100

#define	XDP_DPCD_LANE_COUNT_SET 0x00101

#define	XDP_DPCD_TP_SET 0x00102

#define	XDP_DPCD_TRAINING_LANE0_SET 0x00103

#define	XDP_DPCD_TRAINING_LANE1_SET 0x00104

#define	XDP_DPCD_TRAINING_LANE2_SET 0x00105

#define	XDP_DPCD_TRAINING_LANE3_SET 0x00106

#define	XDP_DPCD_DOWNSPREAD_CTRL 0x00107

#define	XDP_DPCD_ML_CH_CODING_SET 0x00108

#define	XDP_DPCD_I2C_SPEED_CTL_SET 0x00109

#define	XDP_DPCD_EDP_CFG_SET 0x0010A

#define	XDP_DPCD_LINK_QUAL_LANE0_SET 0x0010B

#define	XDP_DPCD_LINK_QUAL_LANE1_SET 0x0010C

#define	XDP_DPCD_LINK_QUAL_LANE2_SET 0x0010D

#define	XDP_DPCD_LINK_QUAL_LANE3_SET 0x0010E

#define	XDP_DPCD_TRAINING_LANE0_1_SET2 0x0010F

#define	XDP_DPCD_TRAINING_LANE2_3_SET2 0x00110

#define	XDP_DPCD_MSTM_CTRL 0x00111

#define	XDP_DPCD_AUDIO_DELAY_7_0 0x00112

#define	XDP_DPCD_AUDIO_DELAY_15_8 0x00113

#define	XDP_DPCD_AUDIO_DELAY_23_6 0x00114

#define	XDP_DPCD_UPSTREAM_DEVICE_DP_PWR_NEED 0x00118

#define	XDP_DPCD_FAUX_MODE_CTRL 0x00120

#define	XDP_DPCD_FAUX_FORWARD_CH_DRIVE_SET 0x00121

#define	XDP_DPCD_BACK_CH_STATUS 0x00122

#define	XDP_DPCD_FAUX_BACK_CH_SYMBOL_ERROR_COUNT 0x00123

#define	XDP_DPCD_FAUX_BACK_CH_TRAINING_PATTERN_TIME 0x00125

#define	XDP_DPCD_TX_GTC_VALUE_7_0 0x00154

#define	XDP_DPCD_TX_GTC_VALUE_15_8 0x00155

#define	XDP_DPCD_TX_GTC_VALUE_23_16 0x00156

#define	XDP_DPCD_TX_GTC_VALUE_31_24 0x00157

#define	XDP_DPCD_RX_GTC_VALUE_PHASE_SKEW_EN 0x00158

#define	XDP_DPCD_TX_GTC_FREQ_LOCK_DONE 0x00159

#define	XDP_DPCD_ADAPTER_CTRL 0x001A0

#define	XDP_DPCD_BRANCH_DEVICE_CTRL 0x001A1

#define	XDP_DPCD_PAYLOAD_ALLOCATE_SET 0x001C0

#define	XDP_DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x001C1

#define	XDP_DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x001C2

DisplayPort Configuration Data: Link/sink status field.
#define	XDP_DPCD_SINK_COUNT 0x00200

#define	XDP_DPCD_DEVICE_SERVICE_IRQ 0x00201

#define	XDP_DPCD_STATUS_LANE_0_1 0x00202

#define	XDP_DPCD_STATUS_LANE_2_3 0x00203

#define	XDP_DPCD_LANE_ALIGN_STATUS_UPDATED 0x00204

#define	XDP_DPCD_SINK_STATUS 0x00205

#define	XDP_DPCD_INTRA_HOP_INDICATION 0x08

#define	XDP_DPCD_ADJ_REQ_LANE_0_1 0x00206

#define	XDP_DPCD_ADJ_REQ_LANE_2_3 0x00207

#define	XDP_DPCD_TRAINING_SCORE_LANE_0 0x00208

#define	XDP_DPCD_TRAINING_SCORE_LANE_1 0x00209

#define	XDP_DPCD_TRAINING_SCORE_LANE_2 0x0020A

#define	XDP_DPCD_TRAINING_SCORE_LANE_3 0x0020B

#define	XDP_DPCD_ADJ_REQ_PC2 0x0020C

#define	XDP_DPCD_FAUX_FORWARD_CH_SYMBOL_ERROR_COUNT 0x0020D

#define	XDP_DPCD_SYMBOL_ERROR_COUNT_LANE_0 0x00210

#define	XDP_DPCD_SYMBOL_ERROR_COUNT_LANE_1 0x00212

#define	XDP_DPCD_SYMBOL_ERROR_COUNT_LANE_2 0x00214

#define	XDP_DPCD_SYMBOL_ERROR_COUNT_LANE_3 0x00216

DisplayPort Configuration Data: Automated testing sub-field.
#define	XDP_DPCD_FAUX_FORWARD_CH_STATUS 0x00280

#define	XDP_DPCD_FAUX_BACK_CH_DRIVE_SET 0x00281

#define	XDP_DPCD_FAUX_BACK_CH_SYM_ERR_COUNT_CTRL 0x00282

#define	XDP_DPCD_PAYLOAD_TABLE_UPDATE_STATUS 0x002C0

#define	XDP_DPCD_VC_PAYLOAD_ID_SLOT(SlotNum) (XDP_DPCD_PAYLOAD_TABLE_UPDATE_STATUS + SlotNum)

DisplayPort Configuration Data: Sink control field.
#define	XDP_DPCD_SET_POWER_DP_PWR_VOLTAGE 0x00600

DisplayPort Configuration Data: Sideband message buffers.
#define	XDP_DPCD_DOWN_REQ 0x01000

#define	XDP_DPCD_UP_REP 0x01200

#define	XDP_DPCD_DOWN_REP 0x01400

#define	XDP_DPCD_UP_REQ 0x01600

DisplayPort Configuration Data: Event status indicator field.
#define	XDP_DPCD_SINK_COUNT_ESI 0x02002

#define	XDP_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x02003

#define	XDP_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x02004

#define	XDP_DPCD_SINK_LINK_SERVICE_IRQ_VECTOR_ESI0 0x02005

#define	XDP_DPCD_SINK_LANE0_1_STATUS 0x0200C

#define	XDP_DPCD_SINK_LANE2_3_STATUS 0x0200D

#define	XDP_DPCD_SINK_ALIGN_STATUS_UPDATED_ESI 0x0200E

#define	XDP_DPCD_SINK_STATUS_ESI 0x0200F

DisplayPort Extended Configuration Data Registers.
#define	XDP_DPCD_EXT_DPCD_REV 0x02200

#define	XDP_DPCD_EXT_DPCD_MAX_LINK_RATE 0x02201

DisplayPort Configuration Data: Field addresses and sizes.
#define	XDP_DPCD_RECEIVER_CAP_FIELD_START XDP_DPCD_REV

#define	XDP_DPCD_RECEIVER_CAP_FIELD_SIZE 0x100

#define	XDP_DPCD_LINK_CFG_FIELD_START XDP_DPCD_LINK_BW_SET

#define	XDP_DPCD_LINK_CFG_FIELD_SIZE 0x100

#define	XDP_DPCD_LINK_SINK_STATUS_FIELD_START XDP_DPCD_SINK_COUNT

#define	XDP_DPCD_LINK_SINK_STATUS_FIELD_SIZE 0x17

DisplayPort Configuration Data: Receiver capability field masks,
shifts, and register values.
#define	XDP_DPCD_REV_MNR_MASK 0x0F

#define	XDP_DPCD_REV_MJR_MASK 0xF0

#define	XDP_DPCD_REV_MJR_SHIFT 4

#define	XDP_DPCD_MAX_LINK_RATE_162GBPS 0x06

#define	XDP_DPCD_MAX_LINK_RATE_270GBPS 0x0A

#define	XDP_DPCD_MAX_LINK_RATE_540GBPS 0x14

#define	XDP_DPCD_MAX_LINK_RATE_810GBPS 0x1E

#define	XDP_DPCD_MAX_LANE_COUNT_MASK 0x1F

#define	XDP_DPCD_MAX_LANE_COUNT_1 0x01

#define	XDP_DPCD_MAX_LANE_COUNT_2 0x02

#define	XDP_DPCD_MAX_LANE_COUNT_4 0x04

#define	XDP_DPCD_POST_LT_ADJ_REQ_SUPPORT_MASK 0x20

#define	XDP_DPCD_TPS3_SUPPORT_MASK 0x40

#define	XDP_DPCD_ENHANCED_FRAME_SUPPORT_MASK 0x80

#define	VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED 0x08

#define	XDP_DPCD_MAX_DOWNSPREAD_MASK 0x01

#define	XDP_DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK 0x40

#define	XDP_DPCD_TPS4_SUPPORT_MASK 0x80

#define	XDP_DPCD_NORP_MASK 0x01

#define	XDP_DPCD_NORP_TYPE_1RP_MASK 0

#define	XDP_DPCD_NORP_TYPE_G2RP_MASK 1

#define	XDP_DPCD_5V_DP_PWR_CAP_MASK 0x20

#define	XDP_DPCD_12V_DP_PWR_CAP_MASK 0x40

#define	XDP_DPCD_18V_DP_PWR_CAP_MASK 0x80

#define	XDP_DPCD_DOWNSP_PRESENT_MASK 0x01

#define	XDP_DPCD_DOWNSP_TYPE_MASK 0x06

#define	XDP_DPCD_DOWNSP_TYPE_SHIFT 1

#define	XDP_DPCD_DOWNSP_TYPE_DP 0x0

#define	XDP_DPCD_DOWNSP_TYPE_AVGA_ADVII 0x1

#define	XDP_DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP 0x2

#define	XDP_DPCD_DOWNSP_TYPE_OTHERS 0x3

#define	XDP_DPCD_DOWNSP_FORMAT_CONV_MASK 0x08

#define	XDP_DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK 0x10

#define	XDP_DPCD_ML_CH_CODING_MASK 0x01

#define	XDP_DPCD_DOWNSP_COUNT_MASK 0x0F

#define	XDP_DPCD_MSA_TIMING_PAR_IGNORED_MASK 0x40

#define	XDP_DPCD_OUI_SUPPORT_MASK 0x80

#define	XDP_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK 0x02

#define	XDP_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK 0x04

#define	XDP_DPCD_RX_PORTX_CAP_0_HBLACK_EXPANSION_CAPABLE_MASK 0x08

#define	XDP_DPCD_RX_PORTX_CAP_0_BUFFER_SIZE_UNIT_MASK 0x10

#define	XDP_DPCD_RX_PORTX_CAP_0_BUFFER_SIZE_PER_PORT_MASK 0x20

#define	XDP_DPCD_RX_PORTX_CAP_1_BUFFER_SIZE_MASK 0xFF

#define	XDP_DPCD_I2C_SPEED_CTL_NONE 0x00

#define	XDP_DPCD_I2C_SPEED_CTL_1KBIPS 0x01

#define	XDP_DPCD_I2C_SPEED_CTL_5KBIPS 0x02

#define	XDP_DPCD_I2C_SPEED_CTL_10KBIPS 0x04

#define	XDP_DPCD_I2C_SPEED_CTL_100KBIPS 0x08

#define	XDP_DPCD_I2C_SPEED_CTL_400KBIPS 0x10

#define	XDP_DPCD_I2C_SPEED_CTL_1MBIPS 0x20

#define	XDP_DPCD_TRAIN_AUX_RD_INT_MASK 0x7F

#define	XDP_DPCD_TRAIN_AUX_RD_INT_100_400US 0x00

#define	XDP_DPCD_TRAIN_AUX_RD_INT_4MS 0x01

#define	XDP_DPCD_TRAIN_AUX_RD_INT_8MS 0x02

#define	XDP_DPCD_TRAIN_AUX_RD_INT_12MS 0x03

#define	XDP_DPCD_TRAIN_AUX_RD_INT_16MS 0x04

#define	XDP_DPCD_TRAIN_AUX_RD_EXT_RX_CAP_FIELD_PRESENT_MASK 0x80

#define	XDP_DPCD_ADAPTOR_CAP_FORCE_LOAD_SENSE_MASK 0x1

#define	XDP_DPCD_ADAPTOR_CAP_ALT_I2C_PATTERN_MASK 0x2

#define	XDP_DPCD_FAUX_CAP_MASK 0x01

#define	XDP_DPCD_MST_CAP_MASK 0x01

#define	XDP_DPCD_MST_SIDEBAND_MSG_CAP 0x02

#define	XDP_DPCD_AV_SYNC_DATA_BLK_AV_GRAN_AG_FACTOR_MASK 0xF

#define	XDP_DPCD_AV_SYNC_DATA_BLK_AV_GRAN_AG_FACTOR_3MS 0x0

#define	XDP_DPCD_AV_SYNC_DATA_BLK_AV_GRAN_AG_FACTOR_2MS 0x1

#define	XDP_DPCD_AV_SYNC_DATA_BLK_AV_GRAN_AG_FACTOR_1MS 0x2

#define	XDP_DPCD_AV_SYNC_DATA_BLK_AV_GRAN_AG_FACTOR_500US 0x3

#define	XDP_DPCD_AV_SYNC_DATA_BLK_AV_GRAN_AG_FACTOR_200US 0x4

#define	XDP_DPCD_AV_SYNC_DATA_BLK_AV_GRAN_AG_FACTOR_100US 0x5

#define	XDP_DPCD_AV_SYNC_DATA_BLK_AV_GRAN_AG_FACTOR_10US 0x6

#define	XDP_DPCD_AV_SYNC_DATA_BLK_AV_GRAN_AG_FACTOR_1US 0x7

#define	XDP_DPCD_AV_SYNC_DATA_BLK_AV_GRAN_VG_FACTOR_MASK 0xF0

#define	XDP_DPCD_AV_SYNC_DATA_BLK_AV_GRAN_VG_FACTOR_3MS 0x0

#define	XDP_DPCD_AV_SYNC_DATA_BLK_AV_GRAN_VG_FACTOR_2MS 0x1

#define	XDP_DPCD_AV_SYNC_DATA_BLK_AV_GRAN_VG_FACTOR_1MS 0x2

#define	XDP_DPCD_AV_SYNC_DATA_BLK_AV_GRAN_VG_FACTOR_500US 0x3

#define	XDP_DPCD_AV_SYNC_DATA_BLK_AV_GRAN_VG_FACTOR_200US 0x4

#define	XDP_DPCD_AV_SYNC_DATA_BLK_AV_GRAN_VG_FACTOR_100US 0x5

#define	XDP_DPCD_AV_SYNC_DATA_BLOCK_01_AUD_DEC_LAT_MASK 0xFF

#define	XDP_DPCD_AV_SYNC_DATA_BLOCK_23_AUD_PP_LAT_MASK 0xFF

#define	XDP_DPCD_AV_SYNC_DATA_BLOCK_4_VID_INTER_LAT_MASK 0xFF

#define	XDP_DPCD_AV_SYNC_DATA_BLOCK_5_VID_PROG_LAT_MASK 0xFF

#define	XDP_DPCD_AV_SYNC_DATA_BLOCK_6_REP_LAT_MASK 0xFF

#define	XDP_DPCD_AV_SYNC_DATA_BLOCK_789_AUD_DEL_INS_MASK 0xFF

#define	XDP_DPCD_RX_GTC_VALUE_X_RX_GTC_VALUE 0xFF

#define	XDP_DPCD_RX_MSTR_REQ_RX_GTC_MSTR_REQ_MASK 0x1

#define	XDP_DPCD_RX_MSTR_REQ_TX_GTC_VALUE_PAHSE_SKEW_EN_MASK 0x2

#define	XDP_DPCD_RX_GTC_FREQ_LOCK_DONE_MASK 0x1

#define	XDP_DPCD_GTC_PHASE_SKEW_OFFSET_X_MASK 0xFF

#define	XDP_DPCD_DSC_SUPPORT_MASK 0x1

#define	XDP_DPCD_DSC_ALGO_REV_DSC_REV_MAJOR_MASK 0xF

#define	XDP_DPCD_DSC_ALGO_REV_DSC_REV_MINOR_MASK 0xF0

#define	XDP_DPCD_DSC_RC_BUF_BLK_SZ_MASK 0x3

#define	XDP_DPCD_DSC_RC_BUF_BLK_SZ_1KB 0x0

#define	XDP_DPCD_DSC_RC_BUF_BLK_SZ_4KB 0x1

#define	XDP_DPCD_DSC_RC_BUF_BLK_SZ_16KB 0x2

#define	XDP_DPCD_DSC_RC_BUF_BLK_SZ_64KB 0x3

#define	XDP_DPCD_DSC_RC_BUF_SZ_MASK 0xF

#define	XDP_DPCD_DSC_SLICE_CAP_1SL_PER_DP_DSC_SINK_DEV_MASK 0x1

#define	XDP_DPCD_DSC_SLICE_CAP_2SL_PER_DP_DSC_SINK_DEV_MASK 0x2

#define	XDP_DPCD_DSC_SLICE_CAP_4SL_PER_DP_DSC_SINK_DEV_MASK 0x8

#define	XDP_DPCD_DSC_SLICE_CAP_6SL_PER_DP_DSC_SINK_DEV_MASK 0x10

#define	XDP_DPCD_DSC_SLICE_CAP_8SL_PER_DP_DSC_SINK_DEV_MASK 0x20

#define	XDP_DPCD_DSC_SLICE_CAP_10SL_PER_DP_DSC_SINK_DEV_MASK 0x40

#define	XDP_DPCD_DSC_SLICE_CAP_12SL_PER_DP_DSC_SINK_DEV_MASK 0x80

#define	XDP_DPCD_DSC_LINE_BUFFER_BIT_DEPTH_MASK 0xF

#define	XDP_DPCD_DSC_LINE_BUFFER_BIT_DEPTH_9BITS 0x0

#define	XDP_DPCD_DSC_LINE_BUFFER_BIT_DEPTH_10BITS 0x1

#define	XDP_DPCD_DSC_LINE_BUFFER_BIT_DEPTH_11BITS 0x2

#define	XDP_DPCD_DSC_LINE_BUFFER_BIT_DEPTH_12BITS 0x3

#define	XDP_DPCD_DSC_LINE_BUFFER_BIT_DEPTH_13BITS 0x4

#define	XDP_DPCD_DSC_LINE_BUFFER_BIT_DEPTH_14BITS 0x5

#define	XDP_DPCD_DSC_LINE_BUFFER_BIT_DEPTH_15BITS 0x6

#define	XDP_DPCD_DSC_LINE_BUFFER_BIT_DEPTH_16BITS 0x7

#define	XDP_DPCD_DSC_LINE_BUFFER_BIT_DEPTH_8BITS 0x8

#define	XDP_DPCD_DSC_BLOCK_PREDICTION_SUPPORT_MASK 0x1

#define	XDP_DPCD_DSC_DECODER_CLR_FRMT_CAP_RGB_MASK 0x1

#define	XDP_DPCD_DSC_DECODER_CLR_FRMT_CAP_YCRCB444_MASK 0x2

#define	XDP_DPCD_DSC_DECODER_CLR_FRMT_CAP_YCRCB422_SIMPLE_MASK 0x4

#define	XDP_DPCD_DSC_DECODER_CLR_FRMT_CAP_YCRCB422_NATIVE_MASK 0x8

#define	XDP_DPCD_DSC_DECODER_CLR_FRMT_CAP_YCRCB420_NATIVE_MASK 0x10

#define	XDP_DPCD_DSC_DECODER_CLR_DEPTH_CAP_8BPC_MASK 0x2

#define	XDP_DPCD_DSC_DECODER_CLR_DEPTH_CAP_10BPC_MASK 0x4

#define	XDP_DPCD_DSC_DECODER_CLR_DEPTH_CAP_12BPC_MASK 0x8

#define	XDP_DPCD_PEAK_DSC_THROUGHPUT_MODE0_MASK 0xF

#define	XDP_DPCD_PEAK_DSC_THROUGHPUT_MODE1_MASK 0xF0

#define	XDP_DPCD_PEAK_DSC_THROUGHPUT_MODEX_NOT_SUPPORTED 0

#define	XDP_DPCD_PEAK_DSC_THROUGHPUT_MODEX_340MPS 1

#define	XDP_DPCD_PEAK_DSC_THROUGHPUT_MODEX_400MPS 2

#define	XDP_DPCD_PEAK_DSC_THROUGHPUT_MODEX_450MPS 3

#define	XDP_DPCD_PEAK_DSC_THROUGHPUT_MODEX_500MPS 4

#define	XDP_DPCD_PEAK_DSC_THROUGHPUT_MODEX_550MPS 5

#define	XDP_DPCD_PEAK_DSC_THROUGHPUT_MODEX_600MPS 6

#define	XDP_DPCD_PEAK_DSC_THROUGHPUT_MODEX_650MPS 7

#define	XDP_DPCD_PEAK_DSC_THROUGHPUT_MODEX_700MPS 8

#define	XDP_DPCD_PEAK_DSC_THROUGHPUT_MODEX_750MPS 9

#define	XDP_DPCD_PEAK_DSC_THROUGHPUT_MODEX_800MPS 10

#define	XDP_DPCD_PEAK_DSC_THROUGHPUT_MODEX_850MPS 11

#define	XDP_DPCD_PEAK_DSC_THROUGHPUT_MODEX_900MPS 12

#define	XDP_DPCD_PEAK_DSC_THROUGHPUT_MODEX_950MPS 13

#define	XDP_DPCD_PEAK_DSC_THROUGHPUT_MODEX_1000MPS 14

#define	XDP_DPCD_PEAK_DSC_THROUGHPUT_MODEX_RSVD 15

#define	XDP_DPCD_DSC_MAX_SLICE_WIDTH_MASK 0xFF

#define	XDP_DPCD_DSC_SLICE_CAP_16SL_PER_DP_DSC_SINK_DEV_MASK 0x1

#define	XDP_DPCD_DSC_SLICE_CAP_20SL_PER_DP_DSC_SINK_DEV_MASK 0x2

#define	XDP_DPCD_DSC_SLICE_CAP_24SL_PER_DP_DSC_SINK_DEV_MASK 0x4

#define	XDP_DPCD_DSC_BPP_INCREMENT_MASK 0x7

#define	XDP_DPCD_DSC_BPP_INCREMENT_1H16BPP 0x0

#define	XDP_DPCD_DSC_BPP_INCREMENT_1H8BPP 0x1

#define	XDP_DPCD_DSC_BPP_INCREMENT_1H4BPP 0x2

#define	XDP_DPCD_DSC_BPP_INCREMENT_1H2BPP 0x3

#define	XDP_DPCD_DSC_BPP_INCREMENT_1BPP 0x4

#define	XDP_DPCD_DOWNSP_X_CAP_TYPE_MASK 0x07

#define	XDP_DPCD_DOWNSP_X_CAP_TYPE_DP 0x0

#define	XDP_DPCD_DOWNSP_X_CAP_TYPE_AVGA 0x1

#define	XDP_DPCD_DOWNSP_X_CAP_TYPE_DVI 0x2

#define	XDP_DPCD_DOWNSP_X_CAP_TYPE_HDMI 0x3

#define	XDP_DPCD_DOWNSP_X_CAP_TYPE_OTHERS 0x4

#define	XDP_DPCD_DOWNSP_X_CAP_TYPE_DPPP 0x5

#define	XDP_DPCD_DOWNSP_X_CAP_HPD_MASK 0x80

#define	XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_MASK 0xF0

#define	XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_SHIFT 4

#define	XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_60 0x1

#define	XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_50 0x2

#define	XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_60 0x3

#define	XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_50 0x4

#define	XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_60 0x5

#define	XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_50 0x7

#define	XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_MASK 0x03

#define	XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_8 0x0

#define	XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_10 0x1

#define	XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_12 0x2

#define	XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_16 0x3

#define	XDP_DPCD_DOWNSP_X_DCAP_HDMI_DPPP_FS2FP_MASK 0x01

#define	XDP_DPCD_DOWNSP_X_DCAP_DVI_DL_MASK 0x02

#define	XDP_DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK 0x04

DisplayPort Configuration Data: Link configuration field masks,
shifts, and register values.
#define	XDP_DPCD_LINK_BW_SET_162GBPS 0x06

#define	XDP_DPCD_LINK_BW_SET_270GBPS 0x0A

#define	XDP_DPCD_LINK_BW_SET_540GBPS 0x14

#define	XDP_DPCD_LINK_BW_SET_810GBPS 0x1E

#define	XDP_DPCD_LANE_COUNT_SET_MASK 0x0F

#define	XDP_DPCD_LANE_COUNT_SET_1 0x01

#define	XDP_DPCD_LANE_COUNT_SET_2 0x02

#define	XDP_DPCD_LANE_COUNT_SET_4 0x04

#define	XDP_DPCD_ENHANCED_FRAME_EN_MASK 0x80

#define	XDP_DPCD_TP_SEL_MASK 0x03

#define	XDP_DPCD_TP_SEL_OFF 0x0

#define	XDP_DPCD_TP_SEL_TP1 0x1

#define	XDP_DPCD_TP_SEL_TP2 0x2

#define	XDP_DPCD_TP_SEL_TP3 0x3

#define	XDP_DPCD_TP_SEL_TP4 0x7

#define	XDP_DPCD_TP_SET_LQP_MASK 0x06

#define	XDP_DPCD_TP_SET_LQP_SHIFT 2

#define	XDP_DPCD_TP_SET_LQP_OFF 0x0

#define	XDP_DPCD_TP_SET_LQP_D102_TEST 0x1

#define	XDP_DPCD_TP_SET_LQP_SER_MES 0x2

#define	XDP_DPCD_TP_SET_LQP_PRBS7 0x3

#define	XDP_DPCD_TP_SET_REC_CLK_OUT_EN_MASK 0x10

#define	XDP_DPCD_TP_SET_SCRAMB_DIS_MASK 0x20

#define	XDP_DPCD_TP_SET_SE_COUNT_SEL_MASK 0xC0

#define	XDP_DPCD_TP_SET_SE_COUNT_SEL_SHIFT 6

#define	XDP_DPCD_TP_SET_SE_COUNT_SEL_DE_ISE 0x0

#define	XDP_DPCD_TP_SET_SE_COUNT_SEL_DE 0x1

#define	XDP_DPCD_TP_SET_SE_COUNT_SEL_ISE 0x2

#define	XDP_DPCD_TRAINING_LANEX_SET_VS_MASK 0x03

#define	XDP_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK 0x04

#define	XDP_DPCD_TRAINING_LANEX_SET_PE_MASK 0x18

#define	XDP_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3

#define	XDP_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK 0x20

#define	XDP_DPCD_SPREAD_AMP_MASK 0x10

#define	XDP_DPCD_MSA_TIMING_PAR_IGNORED_EN_MASK 0x80

#define	XDP_DPCD_TRAINING_LANE_0_2_SET_PC2_MASK 0x03

#define	XDP_DPCD_TRAINING_LANE_0_2_SET_MAX_PC2_MASK 0x04

#define	XDP_DPCD_TRAINING_LANE_1_3_SET_PC2_MASK 0x30

#define	XDP_DPCD_TRAINING_LANE_1_3_SET_PC2_SHIFT 4

#define	XDP_DPCD_TRAINING_LANE_1_3_SET_MAX_PC2_MASK 0x40

#define	XDP_DPCD_MST_EN_MASK 0x01

#define	XDP_DPCD_UP_REQ_EN_MASK 0x02

#define	XDP_DPCD_UP_IS_SRC_MASK 0x04

DisplayPort Configuration Data: Link/sink status field masks, shifts,
and register values.
#define	XDP_DPCD_SINK_COUNT_LOW_MASK 0x3F

#define	XDP_DPCD_SINK_CP_READY_MASK 0x40

#define	XDP_DPCD_SINK_COUNT_HIGH_MASK 0x80

#define	XDP_DPCD_SINK_COUNT_HIGH_LOW_SHIFT 1

#define	XDP_DPCD_STATUS_LANE_0_CR_DONE_MASK 0x01

#define	XDP_DPCD_STATUS_LANE_0_CE_DONE_MASK 0x02

#define	XDP_DPCD_STATUS_LANE_0_SL_DONE_MASK 0x04

#define	XDP_DPCD_STATUS_LANE_1_CR_DONE_MASK 0x10

#define	XDP_DPCD_STATUS_LANE_1_CE_DONE_MASK 0x20

#define	XDP_DPCD_STATUS_LANE_1_SL_DONE_MASK 0x40

#define	XDP_DPCD_STATUS_LANE_2_CR_DONE_MASK 0x01

#define	XDP_DPCD_STATUS_LANE_2_CE_DONE_MASK 0x02

#define	XDP_DPCD_STATUS_LANE_2_SL_DONE_MASK 0x04

#define	XDP_DPCD_STATUS_LANE_3_CR_DONE_MASK 0x10

#define	XDP_DPCD_STATUS_LANE_3_CE_DONE_MASK 0x20

#define	XDP_DPCD_STATUS_LANE_3_SL_DONE_MASK 0x40

#define	XDP_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK 0x01

#define	XDP_DPCD_LANE_ALIGN_STATUS_UPDATED_DOWNSP_STATUS_CHANGED_MASK 0x40

#define	XDP_DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_MASK 0x80

#define	XDP_DPCD_LANE_ALIGN_STATUS_128B_LT_FAILED 0x10

#define	XDP_DPCD_LANE_ALIGN_STATUS_128B_CDS_INTERALIGN_DONE 0x08

#define	XDP_DPCD_LANE_ALIGN_STATUS_128B_EQ_INTERALIGN_DONE 0x04

#define	XDP_DPCD_SINK_STATUS_RX_PORT0_SYNC_STATUS_MASK 0x01

#define	XDP_DPCD_SINK_STATUS_RX_PORT1_SYNC_STATUS_MASK 0x02

#define	XDP_DPCD_ADJ_REQ_LANE_0_2_VS_MASK 0x03

#define	XDP_DPCD_ADJ_REQ_LANE_0_2_PE_MASK 0x0C

#define	XDP_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT 2

#define	XDP_DPCD_ADJ_REQ_LANE_1_3_VS_MASK 0x30

#define	XDP_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT 4

#define	XDP_DPCD_ADJ_REQ_LANE_1_3_PE_MASK 0xC0

#define	XDP_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT 6

#define	XDP_DPCD_ADJ_REQ_LANE_0_FFE_PRESET 0x0F

#define	XDP_DPCD_ADJ_REQ_LANE_1_FFE_PRESET 0xF0

#define	XDP_DPCD_ADJ_REQ_LANE_2_FFE_PRESET 0x0F

#define	XDP_DPCD_ADJ_REQ_LANE_3_FFE_PRESET 0xF0

#define	XDP_DPCD_ADJ_REQ_PC2_LANE_0_MASK 0x03

#define	XDP_DPCD_ADJ_REQ_PC2_LANE_1_MASK 0x0C

#define	XDP_DPCD_ADJ_REQ_PC2_LANE_1_SHIFT 2

#define	XDP_DPCD_ADJ_REQ_PC2_LANE_2_MASK 0x30

#define	XDP_DPCD_ADJ_REQ_PC2_LANE_2_SHIFT 4

#define	XDP_DPCD_ADJ_REQ_PC2_LANE_3_MASK 0xC0

#define	XDP_DPCD_ADJ_REQ_PC2_LANE_3_SHIFT 6

#define	XDP_TX_MAIN_LINK_CHANNEL_CODING_SET

#define	XDP_TX_MAIN_LINK_CHANNEL_CODING_SET_8B_10B_MASK 0x01

#define	XDP_TX_MAIN_LINK_CHANNEL_CODING_SET_128B_132B_MASK 0x02

#define	XDP_TX_TP_SET_TRAINING_AUX_RD_INTERVAL 0x6CC
	Link Training AUX read interval. More...

#define	XDP_TX_VFREQ_STREAM1_LOW 0x6D0
	Vfreq for MST stream1. More...

#define	XDP_TX_VFREQ_STREAM1_HIGH 0x6D4
	Vfreq for MST stream1. More...

#define	XDP_TX_VFREQ_STREAM2_LOW 0x6E4
	Vfreq for MST stream2. More...

#define	XDP_TX_VFREQ_STREAM2_HIGH 0x6E8
	Vfreq for MST stream2. More...

#define	XDP_TX_VFREQ_STREAM3_LOW 0x6EC
	Vfreq for MST stream3. More...

#define	XDP_TX_VFREQ_STREAM3_HIGH 0x6F0
	Vfreq for MST stream3. More...

#define	XDP_TX_VFREQ_STREAM4_LOW 0x6F4
	Vfreq for MST stream4. More...

#define	XDP_TX_VFREQ_STREAM4_HIGH 0x6F8
	Vfreq for MST stream4. More...

#define	XDP_TX_V2_0_CONFIG 0x6E0
	DP v2.1 Config Params. More...

#define	XDP_TX_V2_0_CONFIG_RESET_MASK 0x1003F

#define	XDP_DPCD_128B_132B_SUPPORTED_LINK_RATE 0x02215 /< 128B/132B Supported LinkRates./

#define	XDP_DPCD_TRAINING_AUX_RD_INTERVAL 0x02216 /< AUX Read Interval Set. /

#define	XDP_DPCD_LTTPR_CAPABILITY 0xF0000

#define	XDP_DPCD_LTTPR_REPEATER_CNT 0xF0002

#define	XDP_PHY_REPEATER_MODE 0xF0003

#define	XDP_PHY_LTTPR_BASE 0xF0010

#define	XDP_DPCD_LTTPR_TRAINING_LANE0_SET 0xF0011

#define	XDP_DPCD_LTTPR_STATUS_LANE_0_1 0xF0030

#define	XDP_PHY_LTTPR_PHY_CONFIG_SIZE 0x50

Extended Display Identification Data: Field addresses and sizes.
Address mapping for the Extended Display Identification Data (EDID) of the downstream device.
#define	XDP_SEGPTR_ADDR 0x30

#define	XDP_EDID_ADDR 0x50

#define	XDP_EDID_BLOCK_SIZE 128

#define	XDP_EDID_DTD_DD(Num) (0x36 + (18 * Num))

#define	XDP_EDID_PTM XDP_EDID_DTD_DD(0)

#define	XDP_EDID_EXT_BLOCK_COUNT 0x7E

Extended Display Identification Data: Register offsets for the
Detailed Timing Descriptor (DTD).
#define	XDP_EDID_DTD_PIXEL_CLK_KHZ_LSB 0x00

#define	XDP_EDID_DTD_PIXEL_CLK_KHZ_MSB 0x01

#define	XDP_EDID_DTD_HRES_LSB 0x02

#define	XDP_EDID_DTD_HBLANK_LSB 0x03

#define	XDP_EDID_DTD_HRES_HBLANK_U4 0x04

#define	XDP_EDID_DTD_VRES_LSB 0x05

#define	XDP_EDID_DTD_VBLANK_LSB 0x06

#define	XDP_EDID_DTD_VRES_VBLANK_U4 0x07

#define	XDP_EDID_DTD_HFPORCH_LSB 0x08

#define	XDP_EDID_DTD_HSPW_LSB 0x09

#define	XDP_EDID_DTD_VFPORCH_VSPW_L4 0x0A

#define	XDP_EDID_DTD_XFPORCH_XSPW_U2 0x0B

#define	XDP_EDID_DTD_HIMGSIZE_MM_LSB 0x0C

#define	XDP_EDID_DTD_VIMGSIZE_MM_LSB 0x0D

#define	XDP_EDID_DTD_XIMGSIZE_MM_U4 0x0E

#define	XDP_EDID_DTD_HBORDER 0x0F

#define	XDP_EDID_DTD_VBORDER 0x10

#define	XDP_EDID_DTD_SIGNAL 0x11

Extended Display Identification Data: Masks, shifts, and register
values.
#define	XDP_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK 0x0F

#define	XDP_EDID_DTD_XRES_XBLANK_U4_XRES_MASK 0xF0

#define	XDP_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT 4

#define	XDP_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK 0x0F

#define	XDP_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK 0xF0

#define	XDP_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT 4

#define	XDP_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK 0xC0

#define	XDP_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK 0x30

#define	XDP_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK 0x0C

#define	XDP_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK 0x03

#define	XDP_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT 6

#define	XDP_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT 4

#define	XDP_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT 2

#define	XDP_EDID_DTD_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK 0x0F

#define	XDP_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK 0xF0

#define	XDP_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT 4

#define	XDP_EDID_DTD_SIGNAL_HPOLARITY_MASK 0x02

#define	XDP_EDID_DTD_SIGNAL_VPOLARITY_MASK 0x04

#define	XDP_EDID_DTD_SIGNAL_HPOLARITY_SHIFT 1

#define	XDP_EDID_DTD_SIGNAL_VPOLARITY_SHIFT 2

Stream identification.
Multi-stream transport (MST) definitions.
#define	XDP_TX_STREAM_ID1 1

#define	XDP_TX_STREAM_ID2 2

#define	XDP_TX_STREAM_ID3 3

#define	XDP_TX_STREAM_ID4 4

#define	XDP_TX_AUDIO_CONTROL_LANEX_SET_SHIFT 4

#define	XDP_RX_STREAM_ID1 1

#define	XDP_RX_STREAM_ID2 2

#define	XDP_RX_STREAM_ID3 3

#define	XDP_RX_STREAM_ID4 4

Sideband message codes when the driver is in MST mode.
#define	XDP_SBMSG_LINK_ADDRESS 0x01

#define	XDP_SBMSG_CONNECTION_STATUS_NOTIFY 0x02

#define	XDP_SBMSG_ENUM_PATH_RESOURCES 0x10

#define	XDP_SBMSG_ALLOCATE_PAYLOAD 0x11

#define	XDP_SBMSG_QUERY_PAYLOAD 0x12

#define	XDP_SBMSG_RESOURCE_STATUS_NOTIFY 0x13

#define	XDP_SBMSG_CLEAR_PAYLOAD_ID_TABLE 0x14

#define	XDP_SBMSG_REMOTE_DPCD_READ 0x20

#define	XDP_SBMSG_REMOTE_DPCD_WRITE 0x21

#define	XDP_SBMSG_REMOTE_I2C_READ 0x22

#define	XDP_SBMSG_REMOTE_I2C_WRITE 0x23

#define	XDP_SBMSG_POWER_UP_PHY 0x24

#define	XDP_SBMSG_POWER_DOWN_PHY 0x25

#define	XDP_SBMSG_SINK_EVENT_NOTIFY 0x30

#define	XDP_SBMSG_QUERY_STREAM_ENCRYPT_STATUS 0x38

#define	XDP_SBMSG_NAK_REASON_WRITE_FAILURE 0x01

#define	XDP_SBMSG_NAK_REASON_INVALID_RAD 0x02

#define	XDP_SBMSG_NAK_REASON_CRC_FAILURE 0x03

#define	XDP_SBMSG_NAK_REASON_BAD_PARAM 0x04

#define	XDP_SBMSG_NAK_REASON_DEFER 0x05

#define	XDP_SBMSG_NAK_REASON_LINK_FAILURE 0x06

#define	XDP_SBMSG_NAK_REASON_NO_RESOURCES 0x07

#define	XDP_SBMSG_NAK_REASON_DPCD_FAIL 0x08

#define	XDP_SBMSG_NAK_REASON_I2C_NAK 0x09

#define	XDP_SBMSG_NAK_REASON_ALLOCATE_FAIL 0x0A

Register access macro definitions.
#define	XDp_In32 Xil_In32

#define	XDp_Out32 Xil_Out32

Macro Definition Documentation

#define XDp_GetCoreType ( InstancePtr )

Value:

((InstancePtr)->Config.IsRx \

? XDP_RX : XDP_TX)

This is function determines whether the DisplayPort core, represented by the XDp structure pointed to, is a transmitter (TX) or a receiver (RX).

Parameters

InstancePtr is a pointer to the XDp instance.

Returns: XDP_RX if the core is of type RX. XDP_TX if the core is of type TX.

Note: C-style signature: XDp_CoreType XDp_GetCoreType(XDp *InstancePtr)

Referenced by XDp_CfgInitialize(), XDp_Initialize(), XDp_InterruptHandler(), and XDp_SelfTest().

#define XDP_GUID_NBYTES 16

The number of bytes for the global unique ID.

#define XDP_LANE_COUNT_SET_1 0x01

Lane count of 1.

Referenced by XDp_IsLaneCountValid().

#define XDP_LANE_COUNT_SET_2 0x02

Lane count of 2.

Referenced by XDp_IsLaneCountValid().

#define XDP_LANE_COUNT_SET_4 0x04

Lane count of 4.

Referenced by XDp_IsLaneCountValid().

#define XDP_LINK_BW_SET_162GBPS 0x06

1.62 Gbps link rate.

Referenced by XDp_IsLinkRateValid().

#define XDP_LINK_BW_SET_270GBPS 0x0A

2.70 Gbps link rate.

Referenced by XDp_IsLinkRateValid().

#define XDP_LINK_BW_SET_540GBPS 0x14

5.40 Gbps link rate.

Referenced by XDp_IsLinkRateValid().

#define XDP_LINK_BW_SET_810GBPS 0x1E

8.10 Gbps link rate.

Referenced by XDp_IsLinkRateValid().

#define XDP_LINK_BW_SET_UHBR10 0x01

10Gbps link rate.

Referenced by XDp_CfgInitialize(), and XDp_IsLinkRateValid().

#define XDP_LINK_BW_SET_UHBR135 0x04

13.5Gbps link rate.

Referenced by XDp_CfgInitialize(), and XDp_IsLinkRateValid().

#define XDP_LINK_BW_SET_UHBR20 0x02

20Gbps link rate.

Referenced by XDp_CfgInitialize(), and XDp_IsLinkRateValid().

#define XDP_MAIN_STREAMX_MISC0_BDC_10BPC 0x2

10 bits per component.

#define XDP_MAIN_STREAMX_MISC0_BDC_12BPC 0x3

12 bits per component.

#define XDP_MAIN_STREAMX_MISC0_BDC_16BPC 0x4

16 bits per component.

#define XDP_MAIN_STREAMX_MISC0_BDC_6BPC 0x0

6 bits per component.

#define XDP_MAIN_STREAMX_MISC0_BDC_8BPC 0x1

8 bits per component.

#define XDP_MAIN_STREAMX_MISC0_BDC_MASK 0x000000E0

Bit depth per color component (BDC).

#define XDP_MAIN_STREAMX_MISC0_BDC_SHIFT 5

Shift bits for BDC.

#define XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK 0x00000006

Component format.

#define XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB 0x0

Stream's component format is RGB.

#define XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT 1

Shift bits for component format.

#define XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422 0x1

Stream's component format is YcbCr 4:2:2.

#define XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444 0x2

Stream's component format is YcbCr 4:4:4.

#define XDP_MAX_NPORTS 16

The maximum number of ports connected to a DisplayPort device.

#define XDp_ReadReg	(	BaseAddress,
		RegOffset
	)	XDp_In32((BaseAddress) + (RegOffset))

This is a low-level function that reads from the specified register.

Parameters

BaseAddress	is the base address of the device.
RegOffset	is the register offset to be read from.

Returns: The 32-bit value of the specified register.

Note: C-style signature: u32 XDp_ReadReg(UINTPTR BaseAddress, u32 RegOffset)

#define XDP_RX_NUM_I2C_ENTRIES_PER_PORT 3

The number of I2C user- defined entries in the I2C map of each port.

#define XDP_TX_LINK_BW_SET_SW_UHBR10 0x20

10Gbps link rate.

Referenced by XDp_CfgInitialize(), and XDp_IsLinkRateValid().

#define XDP_TX_LINK_BW_SET_SW_UHBR135 0x22

13.5Gbps link rate.

Referenced by XDp_CfgInitialize(), and XDp_IsLinkRateValid().

#define XDP_TX_LINK_BW_SET_SW_UHBR20 0x24

20Gbps link rate.

Referenced by XDp_CfgInitialize(), and XDp_IsLinkRateValid().

#define XDP_TX_TP_SET_TRAINING_AUX_RD_INTERVAL 0x6CC

Link Training AUX read interval.

#define XDP_TX_V2_0_CONFIG 0x6E0

DP v2.1 Config Params.

#define XDP_TX_VFREQ_STREAM1_HIGH 0x6D4

Vfreq for MST stream1.

#define XDP_TX_VFREQ_STREAM1_LOW 0x6D0

Vfreq for MST stream1.

#define XDP_TX_VFREQ_STREAM2_HIGH 0x6E8

Vfreq for MST stream2.

#define XDP_TX_VFREQ_STREAM2_LOW 0x6E4

Vfreq for MST stream2.

#define XDP_TX_VFREQ_STREAM3_HIGH 0x6F0

Vfreq for MST stream3.

#define XDP_TX_VFREQ_STREAM3_LOW 0x6EC

Vfreq for MST stream3.

#define XDP_TX_VFREQ_STREAM4_HIGH 0x6F8

Vfreq for MST stream4.

#define XDP_TX_VFREQ_STREAM4_LOW 0x6F4

Vfreq for MST stream4.

#define XDp_TxCfgSetRGB	(	InstancePtr,
		Stream
	)

Value:

XDp_TxCfgSetColorEncode((InstancePtr), (Stream), \

XVIDC_CSF_RGB, XVIDC_BT_601, XDP_DR_VESA)

The following functions set the color encoding scheme for a given stream.

Parameters

InstancePtr	is a pointer to the XDp instance.
Stream	is the stream number for which to configure the color encoding scheme for.

Returns: XST_SUCCESS.

Note: C-style signatures: u32 XDp_TxCfgSetRGB(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetSRGB(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetYonly(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetYCbCr422Bt601(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetYCbCr422Bt709(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetYCbCr444Bt601(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetYCbCr444Bt709(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetXvYcc422Bt601(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetXvYcc422Bt709(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetXvYcc444Bt601(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetXvYcc444Bt709(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetAdbRGB(XDp *InstancePtr, u8 Stream)

#define XDp_WriteReg	(	BaseAddress,
		RegOffset,
		Data
	)	XDp_Out32((BaseAddress) + (RegOffset), (Data))

This is a low-level function that writes to the specified register.

Parameters

BaseAddress	is the base address of the device.
RegOffset	is the register offset to write to.
Data	is the 32-bit data to write to the specified register.

Returns: None.

Note: C-style signature: void XDp_WriteReg(UINTPTR BaseAddress, u32 RegOffset, u32 Data)

Typedef Documentation

typedef void(* XDp_IntrHandler)(void *InstancePtr)

Callback type which represents the handler for interrupts.

Parameters

InstancePtr is a pointer to the XDp instance.

Note: None.

typedef void(* XDp_TimerHandler)(void *InstancePtr, u32 MicroSeconds)

Callback type which represents a custom timer wait handler.

This is only used for Microblaze since it doesn't have a native sleep function. To avoid dependency on a hardware timer, the default wait functionality is implemented using loop iterations; this isn't too accurate. If a custom timer handler is used, the user may implement their own wait implementation using a hardware timer (see example/) for better accuracy.

Parameters

InstancePtr	is a pointer to the XDp instance.
MicroSeconds	is the number of microseconds to be passed to the timer function.

Note: None.

Enumeration Type Documentation

enum Dp_Rx_HandlerType

This typedef enumerates the handlers for the the DisplayPort Receiver.

enum XDp_CoreType

This typedef enumerates the RX and TX modes of operation for the DisplayPort core.

enum XDp_DynamicRange

This typedef enumerates the dynamic ranges available to the DisplayPort core.

enum XDp_lt_lane_count

This typedef enumerates the Lane count.

enum XDp_lt_link_rate

This typedef enumerates the Link Rates.

enum XDp_Tx_HandlerType

This typedef enumerates the handlers for the the DisplayPort Transmitter.

enum XDp_Tx_LttprCount

This typedef enumerates the LTTPR count.

enum XDp_Tx_LttprMode

This typedef enumerates the mode of LTTPR.

Function Documentation

void XDp_CfgInitialize	(	XDp *	InstancePtr,
		XDp_Config *	ConfigPtr,
		UINTPTR	EffectiveAddr
	)

This function retrieves the configuration for this DisplayPort instance and fills in the InstancePtr->Config structure.

Parameters

InstancePtr	is a pointer to the XDp instance.
ConfigPtr	is a pointer to the configuration structure that will be used to copy the settings from.
EffectiveAddr	is the device base address in the virtual memory space. If the address translation is not used, then the physical address is passed.

Returns: None.

Note: Unexpected errors may occur if the address mapping is changed after this function is invoked.

References XDp_Config::BaseAddr, XDp::Config, XDp_TxLinkConfig::cr_done_cnt, XDp_TxLinkConfig::cr_done_oldstate, XDp::IsReady, XDp_Tx::LinkConfig, XDp_TxLinkConfig::MaxLaneCount, XDp_Config::MaxLinkRate, XDp_GetCoreType, XDP_LINK_BW_SET_UHBR10, XDP_LINK_BW_SET_UHBR135, XDP_LINK_BW_SET_UHBR20, XDP_TX_LINK_BW_SET_SW_UHBR10, XDP_TX_LINK_BW_SET_SW_UHBR135, and XDP_TX_LINK_BW_SET_SW_UHBR20.

u32 XDp_Initialize ( XDp * InstancePtr )

This function prepares the DisplayPort core for use depending on whether the core is operating in TX or RX mode.

Parameters

InstancePtr is a pointer to the XDp instance.

Returns

XST_SUCCESS if the DisplayPort core was successfully initialized.
XST_FAILURE otherwise.

Note: None.

References XDp::IsReady, and XDp_GetCoreType.

void XDp_InterruptHandler ( XDp * InstancePtr )

This function is the interrupt handler for the XDp driver.

When an interrupt happens, this interrupt handler will check which TX/RX mode of operation the core is running in, and will call the appropriate interrupt handler. The called interrupt handler will first detect what kind of interrupt happened, then decides which callback function to invoke.

Parameters

InstancePtr is a pointer to the XDp instance.

Returns: None.

Note: None.

References XDp::IsReady, and XDp_GetCoreType.

u8 XDp_IsLaneCountValid	(	XDp *	InstancePtr,
		u8	LaneCount
	)

This function checks the validity of the lane count.

Parameters

InstancePtr	is a pointer to the XDp instance.
LaneCount	is the number of lanes to check if valid.

Returns

1 if specified lane count is valid.
0 otherwise, if the lane count specified isn't valid as per spec, or if it exceeds the capabilities of the TX core.

Note: None.

References XDp::Config, XDp_Config::MaxLaneCount, XDP_LANE_COUNT_SET_1, XDP_LANE_COUNT_SET_2, and XDP_LANE_COUNT_SET_4.

u8 XDp_IsLinkRateValid	(	XDp *	InstancePtr,
		u8	LinkRate
	)

This function checks the validity of the link rate.

Parameters

InstancePtr	is a pointer to the XDp instance.
LinkRate	is the link rate to check if valid.

Returns

1 if specified link rate is valid.
0 otherwise, if the link rate specified isn't valid as per spec, or if it exceeds the capabilities of the TX core.

Note: None.

References XDP_LINK_BW_SET_162GBPS, XDP_LINK_BW_SET_270GBPS, XDP_LINK_BW_SET_540GBPS, XDP_LINK_BW_SET_810GBPS, XDP_LINK_BW_SET_UHBR10, XDP_LINK_BW_SET_UHBR135, XDP_LINK_BW_SET_UHBR20, XDP_TX_LINK_BW_SET_SW_UHBR10, XDP_TX_LINK_BW_SET_SW_UHBR135, and XDP_TX_LINK_BW_SET_SW_UHBR20.

XDp_Config * XDp_LookupConfig ( u16 DeviceId )

This function looks for the device configuration based on the unique device ID.

The table XDp_ConfigTable[] contains the configuration information for each device in the system.

Parameters

DeviceId is the unique device ID of the device being looked up.

Returns: A pointer to the configuration table entry corresponding to the given device ID, or NULL if no match is found.

Note: None.

u32 XDp_SelfTest ( XDp * InstancePtr )

This function runs a self-test on the XDp driver/device depending on whether the core is operating in TX or RX mode.

The sanity test checks whether or not all tested registers hold their default reset values.

Parameters

InstancePtr is a pointer to the XDp instance.

Returns

XST_SUCCESS if the self-test passed - all tested registers hold their default reset values.
XST_FAILURE otherwise.

Note: None.

References XDp::IsReady, and XDp_GetCoreType.

void XDp_SetUserTimerHandler	(	XDp *	InstancePtr,
		XDp_TimerHandler	CallbackFunc,
		void *	CallbackRef
	)

This function installs a custom delay/sleep function to be used by the XDp driver.

Parameters

InstancePtr	is a pointer to the XDp instance.
CallbackFunc	is the address to the callback function.
CallbackRef	is the user data item (microseconds to delay) that will be passed to the custom sleep/delay function when it is invoked.

Returns: None.

Note: None.

References XDp::UserTimerPtr, and XDp::UserTimerWaitUs.

void XDp_WaitUs	(	XDp *	InstancePtr,
		u32	MicroSeconds
	)

This function is the delay/sleep function for the XDp driver.

For the Zynq family, there exists native sleep functionality. For MicroBlaze however, there does not exist such functionality. In the MicroBlaze case, the default method for delaying is to use a predetermined amount of loop iterations. This method is prone to inaccuracy and dependent on system configuration; for greater accuracy, the user may supply their own delay/sleep handler, pointed to by InstancePtr->UserTimerWaitUs, which may have better accuracy if a hardware timer is used.

Parameters

InstancePtr	is a pointer to the XDp instance.
MicroSeconds	is the number of microseconds to delay/sleep for.

Returns: None.

Note: None.

References XDp::IsReady, and XDp::UserTimerWaitUs.

Variable Documentation

u8 GuidTable[16][XDP_GUID_NBYTES]

This table contains a list of global unique identifiers (GUIDs) that will be issued when exploring the topology using the algorithm in the XDp_TxFindAccessibleDpDevices function.

XDp_Config XDp_ConfigTable[XPAR_XDP_NUM_INSTANCES]

A table of configuration structures containing the configuration information for each DisplayPort TX core in the system.

Data Structures

Macros

Typedefs

Enumerations

Functions

Variables

Protocol Selection definitions : DP 1.1, DP 1.2, DP 1.4, DP 2.1.

DP generic definitions: Link bandwith and lane count.

DP generic definitions: Bits per color components.

DP generic definitions: Miscellaneous components; color format.

DisplayPort Configuration Data: Receiver capability field.

DisplayPort Configuration Data: Link configuration field.

DisplayPort Configuration Data: Link/sink status field.

DisplayPort Configuration Data: Automated testing sub-field.

DisplayPort Configuration Data: Sink control field.

DisplayPort Configuration Data: Sideband message buffers.

DisplayPort Configuration Data: Event status indicator field.

DisplayPort Extended Configuration Data Registers.

DisplayPort Configuration Data: Field addresses and sizes.

DisplayPort Configuration Data: Receiver capability field masks,

DisplayPort Configuration Data: Link configuration field masks,

DisplayPort Configuration Data: Link/sink status field masks, shifts,

Extended Display Identification Data: Field addresses and sizes.

Extended Display Identification Data: Register offsets for the

Extended Display Identification Data: Masks, shifts, and register

Stream identification.

Sideband message codes when the driver is in MST mode.

Register access macro definitions.

Macro Definition Documentation

Typedef Documentation

Enumeration Type Documentation

Function Documentation

Variable Documentation