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dfeprach
Vitis Drivers API Documentation
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dfeprach
Vitis Drivers API Documentation
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The implementation of the PRACH component's static initialization functionality.
MODIFICATION HISTORY:
Ver Who Date Changes
1.0 dc 03/08/21 Initial release dc 04/06/21 Register with full node name dc 04/07/21 Fix bare metal initialisation dc 04/21/21 Update due to restructured registers 1.1 dc 06/30/21 Doxygen documentation update dc 10/26/21 Make driver R5 compatible 1.2 dc 10/29/21 Update doxygen comments dc 11/01/21 Add multi AddCC, RemoveCC and UpdateCC dc 11/19/21 Update doxygen documentation 1.4 dc 08/18/22 Update IP version number 1.5 dc 12/14/22 Update multiband register arithmetic dc 01/02/23 Multiband registers update 1.6 cog 07/04/23 Add support for SDT 1.7 dc 11/29/23 Add continuous scheduling
Macros | |
| #define | XDFEPRACH_COMPATIBLE_STRING "xlnx,xdfe-nr-prach-2.0" |
| < More... | |
| #define | XDFEPRACH_PLATFORM_DEVICE_DIR "/sys/bus/platform/devices/" |
| Device location in a file system. More... | |
| #define | XDFEPRACH_COMPATIBLE_PROPERTY "compatible" |
| Device tree property. More... | |
| #define | XDFEPRACH_BUS_NAME "platform" |
| System bus name. More... | |
| #define | XDFEPRACH_BASEADDR_PROPERTY "reg" |
| Base address property. More... | |
| #define | XDFEPRACH_NUM_ANTENNA0_CFG "xlnx,num-antenna0" |
| Number of antenna 1-8. More... | |
| #define | XDFEPRACH_NUM_ANTENNA1_CFG "xlnx,num-antenna1" |
| Number of antenna 1-8. More... | |
| #define | XDFEPRACH_NUM_ANTENNA2_CFG "xlnx,num-antenna2" |
| Number of antenna 1-8. More... | |
| #define | XDFEPRACH_NUM_CC_PER_ANTENNA0_CFG "xlnx,num-cc-per-antenna0" |
| Maximum number of CC's per antenna 16. More... | |
| #define | XDFEPRACH_NUM_CC_PER_ANTENNA1_CFG "xlnx,num-cc-per-antenna1" |
| Maximum number of CC's per antenna 16. More... | |
| #define | XDFEPRACH_NUM_CC_PER_ANTENNA2_CFG "xlnx,num-cc-per-antenna2" |
| Maximum number of CC's per antenna 16. More... | |
| #define | XDFEPRACH_NUM_SLOT_CHANNELS0_CFG "xlnx,num-slot-channels0" |
| Number of Parallel Data Channels 1-4. More... | |
| #define | XDFEPRACH_NUM_SLOT_CHANNELS1_CFG "xlnx,num-slot-channels1" |
| Number of Parallel Data Channels 1-4. More... | |
| #define | XDFEPRACH_NUM_SLOT_CHANNELS2_CFG "xlnx,num-slot-channels2" |
| Number of Parallel Data Channels 1-4. More... | |
| #define | XDFEPRACH_NUM_SLOTS0_CFG "xlnx,num-slots0" |
| Number of Antenna TDM slots, per CC 1-8. More... | |
| #define | XDFEPRACH_NUM_SLOTS1_CFG "xlnx,num-slots1" |
| Number of Antenna TDM slots, per CC 1-8. More... | |
| #define | XDFEPRACH_NUM_SLOTS2_CFG "xlnx,num-slots2" |
| Number of Antenna TDM slots, per CC 1-8. More... | |
| #define | XDFEPRACH_NUM_RACH_LINES_CFG "xlnx,num-rach-lanes" |
| Number of RACH output Lanes 1-2. More... | |
| #define | XDFEPRACH_NUM_RACH_CHANNELS_CFG "xlnx,num-rach-channels" |
| Number of RACH Channels channels 1-16. More... | |
| #define | XDFEPRACH_HAS_CONTINUOUS_SCHED_CFG "xlnx,is-always-on" |
| The continuous scheduling is present. More... | |
| #define | XDFEPRACH_HAS_AXIS_CTRL_CFG "xlnx,has-axis-ctrl" |
| The AXIS dynamic scheduling control interface is present. More... | |
| #define | XDFEPRACH_HAS_IRQ_CFG "xlnx,has-irq" |
| The core has an IRQ port enabled. More... | |
| #define | XDFEPRACH_NUM_BANDS_CFG "xlnx,has-irq" |
| The core has an IRQ port enabled. More... | |