| mipicsiss Vitis Drivers API Documentation

- Overview
- Data Structures
- APIs
- File List
- Examples

mipicsiss Documentation

This is main header file of the Xilinx MIPI CSI Rx Subsystem driver.MIPI CSI Rx Subsystem Overview

MIPI CSI Subsystem is collection of IP cores to control, receive and translate data received from a MIPI CSI Transmitter. The MIPI CSI2 Rx Subsystem is a plug-in solution for interfacing with MIPI CSI based image sensors and rest of the video pipeline. It hides all the complexities of programming the underlying cores from end user.

Core Features

MIPI CSI Rx Subsystem supports following features

- Support for 1 to 4 PPI Lanes.
- Line rates ranging from 80 to 1500 Mbps.
- Different data type support(RAW,RGB,YUV).
- AXI IIC support for CCI Interface.
- Using existing AXI IIC for CCI interface support for better understanding & compatibility with other IIC’s (if any) used in the system
- Filtering of packets based on Virtual channel ID.
- Single,Dual,Quad pixel support at output interface compliant to UG934 format.

The GUI in IPI allows for the following configurations

- Lanes ( 1 to 4 )
- Pixel Format (All RAW and RGB, only YUV422 8bit)
- Virtual Channel (to filter or allow all from interlaced streams)
- Number of Pixels per clock (1, 2, 4)
- DPHY with/without Register interface
- Line Rate
- Buffer Depth
- Embedded Non Image data (if needed)
- Add IIC to subsystem (if required)

The IIC can be added if the system doesn't contain an IIC or if a dedicated IIC is to be used for MIPI CSI Rx Subsystem. In order to reduce resource usage, the DPHY can be configured to be without register interface with fixed functions. Static configuration parameters are stored in xcsiss_g.c file that gets generated when compiling the board support package (BSP). A table is defined where each entry contains configuration information for the instances of the subsystem in the design. This information includes the elected configuration, sub-cores used and their device ID, base addresses of memory mapped devices and address range available for subsystem frame/field buffers.

The subsystem driver itself always includes the full software stack irrespective of the configuration selected. Generic API's are provided to interact with the subsystem and/or with the included sub -cores. At run-time the subsystem will query the static configuration and configures itself for supported use cases

The subsystem driver provides an abstraction on top of the CSI and DPHY drivers.

The IIC instance (if present) is shared with application and can be controlled using the AXI IIC driver.

Software Initialization & Configuration

The application needs to do following steps in order for preparing the MIPI CSI2 Rx Subsystem core to be ready.

- Call XCsiSs_LookupConfig using a device ID to find the core configuration.
- Call XCsiSs_CfgInitialize to initialize the device and the driver instance associated with it.

Interrupts

The XCsiSs_SetCallBack() is used to register the call back functions for MIPI CSI2 Rx Subsystem driver with the corresponding handles

Virtual Memory

This driver supports Virtual Memory. The RTOS is responsible for calculating the correct device base address in Virtual Memory space.

Threads

This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.

Asserts

Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that application developers leave asserts on during development.

Building the driver

The MIPI CSI2 Rx Subsystem driver is composed of source files and depends on the CSI and DPHY drivers. The IIC driver is pulled in if the the IIC instance is enabled. The DPHY driver is pulled in only if the register interface has been enabled for it.Otherwise the CSI driver and subsystem files are built.

    MODIFICATION HISTORY:

    Ver Who Date     Changes

    1.0 vsa 07/25/15 Initial release
    1.1 sss 08/17/16 Added 64 bit support
        sss 08/29/16 Renamed SubCore to CsiRxSsSubCore
        ms  01/23/17 Modified xil_printf statement in main function for all
                     examples to ensure that "Successfully ran" and "Failed"
                     strings are available in all examples. This is a fix
                     for CR-965028.
        ms  03/17/17 Added readme.txt file in examples folder for doxygen
                     generation.