| dp14txss Vitis Drivers API Documentation

- Overview
- Data Structures
- APIs
- File List

dp14txss Documentation

This is the main header file for Xilinx DisplayPort Transmitter Subsystem core. It abstracts Subsystem cores and provides high level API's to application developer.

Core Features

For a full description of DisplayPort Transmitter Subsystem core, please see the hardware specification.

Software Initialization & Configuration

The application needs to do following steps in order for preparing the DisplayPort Transmitter Subsystem core to be ready.

- Call XDpTxSs_LookupConfig using a device ID to find the core configuration.
- Call XDpTxSs_CfgInitialize to initialize the device and the driver instance associated with it.

Interrupts

The DisplayPort TX Subsystem driver provides the interrupt handlers

- XDpTxSs_DpIntrHandler
- XDpTxSs_HdcpIntrHandler
- XDpTxSs_TmrCtrIntrHandler, for handling the interrupt from the DisplayPort, optional HDCP and Timer Counter sub-cores respectively. The users of this driver have to register this handler with the interrupt system and provide the callback functions by using XDpTxSs_SetCallBack API.

Virtual Memory

This driver supports Virtual Memory. The RTOS is responsible for calculating the correct device base address in Virtual Memory space.

Threads

This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.

Asserts

Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that users leave asserts on during development.

Building the driver

The DisplayPort Transmitter Subsystem driver is composed of several source files. This allows the user to build and link only those parts of the driver that are necessary.

    MODIFICATION HISTORY:

    Ver  Who Date     Changes

    1.00 sha 01/29/15 Initial release.
    1.00 sha 07/21/15 Included renamed sub-cores header files.
    2.00 sha 08/07/15 Added new handler types: lane count, link rate,
                      pre-emphasis voltage swing adjust and set MSA.
                      Added support for customized main stream attributes.
                      Added function: XDpTxSs_SetHasRedriverInPath.
                      Added HDCP support data structure.
    2.00 sha 09/28/15 Added HDCP and Timer Counter functions.
    3.0  sha 02/19/16 Added handler type as enums for HDCP:
                      XDPTXSS_HANDLER_HDCP_RPTR_DWN_STRM_RDY,
                      XDPTXSS_HANDLER_HDCP_RPTR_EXCHG.
                      Added function: XDpTxSs_ReadDownstream,
                      XDpTxSs_HandleTimeout.
    4.0  aad 05/13/16 Expose API to set (a)synchronous clock mode from DP driver.
    4.1  als 08/08/16 Synchronize with new HDCP APIs.
         aad 09/06/16 Updates to support 64-bit base addresses.
         ms  01/23/17 Modified xil_printf statement in main function for all
                      examples to ensure that "Successfully ran" and "Failed"
                      strings are available in all examples. This is a fix
                      for CR-965028.
         ms  03/17/17 Modified readme.txt file in examples folder for doxygen
                      generation.
    5.0  tu  08/10/17 Adjusted BS symbol for equal timing
    5.0  tu  09/08/17 Added two interrupt handler that addresses driver's
                      internal callback function of application
                      DrvHpdEventHandler and DrvHpdPulseHandler
                      Added HPD user data stucture XDpTxSs_UsrHpdPulseData
                      and XDpTxSs_UsrHpdEventData
    5.0  jb  02/21/19 Added HDCP22 support.
                                            Made the Timer counter available for both HDCP1x and 22.
    6.4  rg  09/01/20 Added handler type as enum for extended packet transmit
                      done interrupt.
    6.4  rg  09/26/20 Added support for YUV420 color format.