| devcfg Vitis Drivers API Documentation

- Overview
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Data Structures | Macros | Typedefs | Functions | Variables
Overview

## Data Structures
struct | XDcfg_Config
| This typedef contains configuration information for the device. More...
struct | XDcfg
| The XDcfg driver instance data. More...

## Macros
#define | XDcfg_Unlock(InstancePtr)
| Unlock the Device Config Interface block. More...
#define | XDcfg_GetPsVersion(InstancePtr)
| Get the version number of the PS from the Miscellaneous Control Register. More...
#define | XDcfg_ReadMultiBootConfig(InstancePtr)
| Read the multiboot config register value. More...
#define | XDcfg_SelectIcapInterface(InstancePtr)
| Selects ICAP interface for reconfiguration after the initial configuration of the PL. More...
#define | XDcfg_SelectPcapInterface(InstancePtr)
| Selects PCAP interface for reconfiguration after the initial configuration of the PL. More...
#define | XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF
| Invalid DMA address. More...
#define | XDCFG_UNLOCK_DATA 0x757BDF0D
| First APB access data. More...
#define | XDCFG_BASE_ADDRESS 0xF8007000
| Device Config base address. More...
#define | XDCFG_CONFIG_RESET_VALUE 0x508
| Config reg reset value. More...
#define | XDcfg_ReadReg(BaseAddr, RegOffset) Xil_In32((BaseAddr) + (RegOffset))
| Read the given register. More...
#define | XDcfg_WriteReg(BaseAddr, RegOffset, Data) Xil_Out32((BaseAddr) + (RegOffset), (Data))
| Write to the given register. More...

## Typedefs
typedef void(* | XDcfg_IntrHandler )(void *CallBackRef, u32 Status)
| The handler data type allows the user to define a callback function to respond to interrupt events in the system. More...

## Functions
int | XDcfg_CfgInitialize (XDcfg *InstancePtr, XDcfg_Config *ConfigPtr, u32 EffectiveAddress)
| Initialize the Device Config Interface driver. More...
void | XDcfg_EnablePCAP (XDcfg *InstancePtr)
| The functions enables the PCAP interface by setting the PCAP mode bit in the control register. More...
void | XDcfg_DisablePCAP (XDcfg *InstancePtr)
| The functions disables the PCAP interface by clearing the PCAP mode bit in the control register. More...
void | XDcfg_SetControlRegister (XDcfg *InstancePtr, u32 Mask)
| The function sets the contents of the Control Register. More...
void | XDcfg_ClearControlRegister (XDcfg *InstancePtr, u32 Mask)
| The function Clears the specified bit positions of the Control Register. More...
u32 | XDcfg_GetControlRegister (XDcfg *InstancePtr)
| The function reads the contents of the Control Register. More...
void | XDcfg_SetLockRegister (XDcfg *InstancePtr, u32 Data)
| The function sets the contents of the Lock Register. More...
u32 | XDcfg_GetLockRegister (XDcfg *InstancePtr)
| The function reads the contents of the Lock Register. More...
void | XDcfg_SetConfigRegister (XDcfg *InstancePtr, u32 Data)
| The function sets the contents of the Configuration Register with the given value. More...
u32 | XDcfg_GetConfigRegister (XDcfg *InstancePtr)
| The function reads the contents of the Configuration Register with the given value. More...
void | XDcfg_SetStatusRegister (XDcfg *InstancePtr, u32 Data)
| The function sets the contents of the Status Register. More...
u32 | XDcfg_GetStatusRegister (XDcfg *InstancePtr)
| The function reads the contents of the Status Register. More...
void | XDcfg_SetRomShadowRegister (XDcfg *InstancePtr, u32 Data)
| The function sets the contents of the ROM Shadow Control Register. More...
u32 | XDcfg_GetSoftwareIdRegister (XDcfg *InstancePtr)
| The function reads the contents of the Software ID Register. More...
void | XDcfg_SetMiscControlRegister (XDcfg *InstancePtr, u32 Mask)
| The function sets the bit mask for the feature in Miscellaneous Control Register. More...
u32 | XDcfg_GetMiscControlRegister (XDcfg *InstancePtr)
| The function reads the contents of the Miscellaneous Control Register. More...
u32 | XDcfg_IsDmaBusy (XDcfg *InstancePtr)
| This function checks if DMA command queue is full. More...
void | XDcfg_InitiateDma (XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr, u32 SrcWordLength, u32 DestWordLength)
| This function initiates the DMA transfer. More...
u32 | XDcfg_Transfer (XDcfg *InstancePtr, void *SourcePtr, u32 SrcWordLength, void *DestPtr, u32 DestWordLength, u32 TransferType)
| This function starts the DMA transfer. More...
XDcfg_Config * | XDcfg_LookupConfig (u16 DeviceId)
| Lookup the device configuration based on the unique device ID. More...
int | XDcfg_SelfTest (XDcfg *InstancePtr)
| Run a self-test on the Device Configuration Interface. More...
void | XDcfg_IntrEnable (XDcfg *InstancePtr, u32 Mask)
| This function enables the specified interrupts in the device. More...
void | XDcfg_IntrDisable (XDcfg *InstancePtr, u32 Mask)
| This function disables the specified interrupts in the device. More...
u32 | XDcfg_IntrGetEnabled (XDcfg *InstancePtr)
| This function returns the enabled interrupts read from the Interrupt Mask Register. More...
u32 | XDcfg_IntrGetStatus (XDcfg *InstancePtr)
| This function returns the interrupt status read from Interrupt Status Register. More...
void | XDcfg_IntrClear (XDcfg *InstancePtr, u32 Mask)
| This function clears the specified interrupts in the Interrupt Status Register. More...
void | XDcfg_InterruptHandler (XDcfg *InstancePtr)
| The interrupt handler for the Device Config Interface. More...
void | XDcfg_SetHandler (XDcfg *InstancePtr, void *CallBackFunc, void *CallBackRef)
| This function sets the handler that will be called when an event (interrupt) occurs that needs application's attention. More...
void | XDcfg_ResetHw (u32 BaseAddr)
| This function perform the reset sequence to the given devcfg interface by configuring the appropriate control bits in the devcfg specifc registers the devcfg reset squence involves the following steps Disable all the interuupts Clear the status Update relevant config registers with reset values Disbale the looopback mode and pcap rate enable. More...

## Variables
XDcfg_Config | XDcfg_ConfigTable [1]
| This table contains configuration information for each Device Config Interface instance in the system. More...

## Register Map
Offsets of registers from the start of the device
#define | XDCFG_CTRL_OFFSET 0x00
| Control Register. More...
#define | XDCFG_LOCK_OFFSET 0x04
| Lock Register. More...
#define | XDCFG_CFG_OFFSET 0x08
| Configuration Register. More...
#define | XDCFG_INT_STS_OFFSET 0x0C
| Interrupt Status Register. More...
#define | XDCFG_INT_MASK_OFFSET 0x10
| Interrupt Mask Register. More...
#define | XDCFG_STATUS_OFFSET 0x14
| Status Register. More...
#define | XDCFG_DMA_SRC_ADDR_OFFSET 0x18
| DMA Source Address Register. More...
#define | XDCFG_DMA_DEST_ADDR_OFFSET 0x1C
| DMA Destination Address Reg. More...
#define | XDCFG_DMA_SRC_LEN_OFFSET 0x20
| DMA Source Transfer Length. More...
#define | XDCFG_DMA_DEST_LEN_OFFSET 0x24
| DMA Destination Transfer. More...
#define | XDCFG_ROM_SHADOW_OFFSET 0x28
| DMA ROM Shadow Register. More...
#define | XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C
| Multi BootAddress Pointer. More...
#define | XDCFG_SW_ID_OFFSET 0x30
| Software ID Register. More...
#define | XDCFG_UNLOCK_OFFSET 0x34
| Unlock Register. More...
#define | XDCFG_MCTRL_OFFSET 0x80
| Miscellaneous Control Reg. More...

## Control Register Bit definitions
#define | XDCFG_CTRL_FORCE_RST_MASK 0x80000000
| Force into Secure Reset. More...
#define | XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000
| Program signal to Reset FPGA. More...
#define | XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000
| Control PL POR timer. More...
#define | XDCFG_CTRL_PCAP_PR_MASK 0x08000000
| Enable PCAP for PR. More...
#define | XDCFG_CTRL_PCAP_MODE_MASK 0x04000000
| Enable PCAP. More...
#define | XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000
| Enable PCAP send data to FPGA every 4 PCAP cycles. More...
#define | XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000
| Multiboot Enable. More...
#define | XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000
| JTAG Chain Disable. More...
#define | XDCFG_CTRL_USER_MODE_MASK 0x00008000
| User Mode Mask. More...
#define | XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000
| AES key source. More...
#define | XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00
| AES Enable Mask. More...
#define | XDCFG_CTRL_SEU_EN_MASK 0x00000100
| SEU Enable Mask. More...
#define | XDCFG_CTRL_SEC_EN_MASK 0x00000080
| Secure/Non Secure Status mask. More...
#define | XDCFG_CTRL_SPNIDEN_MASK 0x00000040
| Secure Non Invasive Debug Enable. More...
#define | XDCFG_CTRL_SPIDEN_MASK 0x00000020
| Secure Invasive Debug Enable. More...
#define | XDCFG_CTRL_NIDEN_MASK 0x00000010
| Non-Invasive Debug Enable. More...
#define | XDCFG_CTRL_DBGEN_MASK 0x00000008
| Invasive Debug Enable. More...
#define | XDCFG_CTRL_DAP_EN_MASK 0x00000007
| DAP Enable Mask. More...

## Lock register bit definitions
#define | XDCFG_LOCK_AES_EFUSE_MASK 0x00000010
| Lock AES Efuse bit. More...
#define | XDCFG_LOCK_AES_EN_MASK 0x00000008
| Lock AES_EN update. More...
#define | XDCFG_LOCK_SEU_MASK 0x00000004
| Lock SEU_En update. More...
#define | XDCFG_LOCK_SEC_MASK 0x00000002
| Lock SEC_EN and USER_MODE. More...
#define | XDCFG_LOCK_DBG_MASK 0x00000001
| This bit locks security config including: DAP_En, DBGEN,, NIDEN, SPNIEN. More...

## Config Register Bit definitions
#define | XDCFG_CFG_RFIFO_TH_MASK 0x00000C00
| Read FIFO Threshold Mask. More...
#define | XDCFG_CFG_WFIFO_TH_MASK 0x00000300
| Write FIFO Threshold Mask. More...
#define | XDCFG_CFG_RCLK_EDGE_MASK 0x00000080
| Read data active clock edge. More...
#define | XDCFG_CFG_WCLK_EDGE_MASK 0x00000040
| Write data active clock edge. More...
#define | XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020
| Disable Source address increment mask. More...
#define | XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010
| Disable Destination address increment mask. More...

## Interrupt Status/Mask Register Bit definitions
#define | XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000
| Tri-state IO during HIZ. More...
#define | XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000
| First configuration done. More...
#define | XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000
| Global power down. More...
#define | XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000
| Tri-state IO during configuration. More...
#define | XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000
| PL configuration reset. More...
#define | XDCFG_IXR_AXI_WTO_MASK 0x00800000
| AXI Write Address or Data or response timeout. More...
#define | XDCFG_IXR_AXI_WERR_MASK 0x00400000
| AXI Write response error. More...
#define | XDCFG_IXR_AXI_RTO_MASK 0x00200000
| AXI Read Address or response timeout. More...
#define | XDCFG_IXR_AXI_RERR_MASK 0x00100000
| AXI Read response error. More...
#define | XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000
| Rx FIFO Overflow. More...
#define | XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000
| Tx FIFO less than threshold. More...
#define | XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000
| Rx FIFO greater than threshold. More...
#define | XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000
| Illegal DMA command. More...
#define | XDCFG_IXR_DMA_Q_OV_MASK 0x00004000
| DMA command queue overflow. More...
#define | XDCFG_IXR_DMA_DONE_MASK 0x00002000
| DMA Command Done. More...
#define | XDCFG_IXR_D_P_DONE_MASK 0x00001000
| DMA and PCAP transfers Done. More...
#define | XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800
| PCAP to DMA transfer length error. More...
#define | XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040
| HMAC error mask. More...
#define | XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020
| SEU Error mask. More...
#define | XDCFG_IXR_PCFG_POR_B_MASK 0x00000010
| FPGA POR mask. More...
#define | XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008
| FPGA Reset mask. More...
#define | XDCFG_IXR_PCFG_DONE_MASK 0x00000004
| Done Signal Mask. More...
#define | XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002
| Detect Positive edge of Init Signal. More...
#define | XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001
| Detect Negative edge of Init Signal. More...
#define | XDCFG_IXR_ERROR_FLAGS_MASK
#define | XDCFG_IXR_ALL_MASK 0x00F7F8EF

## Status Register Bit definitions
#define | XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000
| DMA command Queue full. More...
#define | XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000
| DMA command Queue empty. More...
#define | XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000
| Number of completed DMA transfers. More...
#define | XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000
| Rx FIFO level. More...
#define | XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000
| Tx FIFO level. More...
#define | XDCFG_STATUS_PSS_GTS_USR_B 0x00000800
| Tri-state IO during HIZ. More...
#define | XDCFG_STATUS_PSS_FST_CFG_B 0x00000400
| First PL config done. More...
#define | XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200
| Global power down. More...
#define | XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100
| Tri-state IO during config. More...
#define | XDCFG_STATUS_SECURE_RST_MASK 0x00000080
| Secure Reset POR Status. More...
#define | XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040
| Illegal APB access. More...
#define | XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020
| PL config reset status. More...
#define | XDCFG_STATUS_PCFG_INIT_MASK 0x00000010
| FPGA Init Status. More...
#define | XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
| BBRAM key disable. More...
#define | XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004
| Efuse Security Enable Status. More...
#define | XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002
| EFuse JTAG Disable status. More...

## DMA Source/Destination Transfer Length Register Bit definitions
#define | XDCFG_DMA_LEN_MASK 0x7FFFFFF
| Length Mask. More...

## Miscellaneous Control Register Bit definitions
#define | XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000
| PS Version Mask. More...
#define | XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28
| PS Version Shift. More...
#define | XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010
| PCAP loopback mask. More...

## FIFO Threshold Bit definitions
#define | XDCFG_CFG_FIFO_QUARTER 0x0
| Quarter empty. More...
#define | XDCFG_CFG_FIFO_HALF 0x1
| Half empty. More...
#define | XDCFG_CFG_FIFO_3QUARTER 0x2
| 3/4 empty More...
#define | XDCFG_CFG_FIFO_EMPTY 0x4
| Empty. More...

## Macro Definition Documentation

#define XDCFG_BASE_ADDRESS 0xF8007000

Device Config base address.

#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010

Disable Destination address increment mask.

#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020

Disable Source address increment mask.

#define XDCFG_CFG_FIFO_3QUARTER 0x2

3/4 empty

#define XDCFG_CFG_FIFO_EMPTY 0x4

Empty.

#define XDCFG_CFG_FIFO_HALF 0x1

Half empty.

#define XDCFG_CFG_FIFO_QUARTER 0x0

Quarter empty.

#define XDCFG_CFG_OFFSET 0x08

Configuration Register.

Referenced by XDcfg_GetConfigRegister(), XDcfg_ResetHw(), and XDcfg_SetConfigRegister().

#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080

Read data active clock edge.

#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00

Read FIFO Threshold Mask.

#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040

Write data active clock edge.

#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300

Write FIFO Threshold Mask.

#define XDCFG_CONFIG_RESET_VALUE 0x508

Config reg reset value.

Referenced by XDcfg_ResetHw().

#define XDCFG_CTRL_DAP_EN_MASK 0x00000007

DAP Enable Mask.

#define XDCFG_CTRL_DBGEN_MASK 0x00000008

Invasive Debug Enable.

#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000

Force into Secure Reset.

#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000

JTAG Chain Disable.

#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000

Multiboot Enable.

#define XDCFG_CTRL_NIDEN_MASK 0x00000010

Non-Invasive Debug Enable.

Referenced by XDcfg_SelfTest().

#define XDCFG_CTRL_OFFSET 0x00

Control Register.

Referenced by XDcfg_ClearControlRegister(), XDcfg_DisablePCAP(), XDcfg_EnablePCAP(), XDcfg_GetControlRegister(), XDcfg_ResetHw(), XDcfg_SetControlRegister(), and XDcfg_Transfer().

#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000

Enable PCAP.

Referenced by XDcfg_DisablePCAP(), and XDcfg_EnablePCAP().

#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000

Enable PCAP for PR.

Referenced by XDcfgInterruptExample(), and XDcfgPolledExample().

#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000

Enable PCAP send data to FPGA every 4 PCAP cycles.

Referenced by XDcfg_ResetHw(), and XDcfg_Transfer().

#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00

AES Enable Mask.

#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000

AES key source.

#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000

Control PL POR timer.

#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000

Program signal to Reset FPGA.

#define XDCFG_CTRL_SEC_EN_MASK 0x00000080

Secure/Non Secure Status mask.

#define XDCFG_CTRL_SEU_EN_MASK 0x00000100

SEU Enable Mask.

#define XDCFG_CTRL_SPIDEN_MASK 0x00000020

Secure Invasive Debug Enable.

#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040

Secure Non Invasive Debug Enable.

#define XDCFG_CTRL_USER_MODE_MASK 0x00008000

User Mode Mask.

#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C

DMA Destination Address Reg.

Referenced by XDcfg_InitiateDma(), and XDcfg_ResetHw().

#define XDCFG_DMA_DEST_LEN_OFFSET 0x24

DMA Destination Transfer.

Referenced by XDcfg_InitiateDma(), and XDcfg_ResetHw().

#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF

Invalid DMA address.

Referenced by XDcfg_GetConfigReg(), XDcfgInterruptExample(), and XDcfgPolledExample().

#define XDCFG_DMA_LEN_MASK 0x7FFFFFF

Length Mask.

#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18

DMA Source Address Register.

Referenced by XDcfg_InitiateDma(), and XDcfg_ResetHw().

#define XDCFG_DMA_SRC_LEN_OFFSET 0x20

DMA Source Transfer Length.

Referenced by XDcfg_InitiateDma(), and XDcfg_ResetHw().

#define XDcfg_GetPsVersion | ( |  | InstancePtr | ) |

Value:
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
XDCFG_MCTRL_OFFSET)) & \
XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
PS Version Shift.
Definition: xdevcfg_hw.h:389
XDCFG_MCTRL_OFFSET
#define XDCFG_MCTRL_OFFSET
Miscellaneous Control Reg.
Definition: xdevcfg_hw.h:67
XDcfg_ReadReg
#define XDcfg_ReadReg(BaseAddr, RegOffset)
Read the given register.
Definition: xdevcfg_hw.h:432
XDCFG_MCTRL_PCAP_PS_VERSION_MASK
#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK
PS Version Mask.
Definition: xdevcfg_hw.h:388

Get the version number of the PS from the Miscellaneous Control Register.

Parameters

  InstancePtr | is a pointer to the instance of XDcfg driver.

Returns
  Version of the PS.

Note
  C-style signature: void XDcfg_GetPsVersion(XDcfg* InstancePtr)

#define XDCFG_INT_MASK_OFFSET 0x10

Interrupt Mask Register.

Referenced by XDcfg_IntrDisable(), XDcfg_IntrEnable(), XDcfg_IntrGetEnabled(), and XDcfg_ResetHw().

#define XDCFG_INT_STS_OFFSET 0x0C

Interrupt Status Register.

Referenced by XDcfg_InterruptHandler(), XDcfg_IntrClear(), XDcfg_IntrGetStatus(), and XDcfg_ResetHw().

#define XDCFG_IXR_AXI_RERR_MASK 0x00100000

AXI Read response error.

#define XDCFG_IXR_AXI_RTO_MASK 0x00200000

AXI Read Address or response timeout.

#define XDCFG_IXR_AXI_WERR_MASK 0x00400000

AXI Write response error.

#define XDCFG_IXR_AXI_WTO_MASK 0x00800000

AXI Write Address or Data or response timeout.

#define XDCFG_IXR_D_P_DONE_MASK 0x00001000

DMA and PCAP transfers Done.

Referenced by XDcfg_GetConfigReg(), XDcfgInterruptExample(), and XDcfgPolledExample().

#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000

Illegal DMA command.

#define XDCFG_IXR_DMA_DONE_MASK 0x00002000

DMA Command Done.

Referenced by XDcfg_GetConfigReg(), XDcfgInterruptExample(), and XDcfgPolledExample().

#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000

DMA command queue overflow.

#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800

PCAP to DMA transfer length error.

#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008

FPGA Reset mask.

#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004

Done Signal Mask.

Referenced by XDcfg_GetConfigReg(), XDcfgInterruptExample(), and XDcfgPolledExample().

#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040

HMAC error mask.

#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001

Detect Negative edge of Init Signal.

#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002

Detect Positive edge of Init Signal.

#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010

FPGA POR mask.

#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020

SEU Error mask.

#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000

PL configuration reset.

#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000

First configuration done.

#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000

Global power down.

#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000

Tri-state IO during configuration.

#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000

Tri-state IO during HIZ.

#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000

Rx FIFO greater than threshold.

#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000

Rx FIFO Overflow.

#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000

Tx FIFO less than threshold.

#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010

Lock AES Efuse bit.

#define XDCFG_LOCK_AES_EN_MASK 0x00000008

Lock AES_EN update.

#define XDCFG_LOCK_DBG_MASK 0x00000001

This bit locks security config including: DAP_En, DBGEN,, NIDEN, SPNIEN.

#define XDCFG_LOCK_OFFSET 0x04

Lock Register.

Referenced by XDcfg_GetLockRegister(), and XDcfg_SetLockRegister().

#define XDCFG_LOCK_SEC_MASK 0x00000002

Lock SEC_EN and USER_MODE.

#define XDCFG_LOCK_SEU_MASK 0x00000004

Lock SEU_En update.

#define XDCFG_MCTRL_OFFSET 0x80

Miscellaneous Control Reg.

Referenced by XDcfg_GetMiscControlRegister(), XDcfg_ResetHw(), XDcfg_SetMiscControlRegister(), and XDcfg_Transfer().

#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010

PCAP loopback mask.

Referenced by XDcfg_ResetHw(), and XDcfg_Transfer().

#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000

PS Version Mask.

#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28

PS Version Shift.

#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C

Multi BootAddress Pointer.

#define XDcfg_ReadMultiBootConfig | ( |  | InstancePtr | ) |

Value:
XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
XDCFG_MULTIBOOT_ADDR_OFFSET)
XDcfg_ReadReg
#define XDcfg_ReadReg(BaseAddr, RegOffset)
Read the given register.
Definition: xdevcfg_hw.h:432
XDCFG_MULTIBOOT_ADDR_OFFSET
#define XDCFG_MULTIBOOT_ADDR_OFFSET
Multi BootAddress Pointer.
Definition: xdevcfg_hw.h:64

Read the multiboot config register value.

Parameters

  InstancePtr | is a pointer to the instance of XDcfg driver.

Returns
  None.

Note
  C-style signature: u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr)

#define XDcfg_ReadReg | ( |  | BaseAddr,
|  |  | RegOffset
| ) |  | Xil_In32((BaseAddr) + (RegOffset))

Read the given register.

Parameters

  BaseAddr | is the base address of the device
  RegOffset | is the register offset to be read

Returns
  The 32-bit value of the register

Note
  C-style signature: u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)

Referenced by XDcfg_ClearControlRegister(), XDcfg_DisablePCAP(), XDcfg_EnablePCAP(), XDcfg_GetConfigReg(), XDcfg_GetConfigRegister(), XDcfg_GetControlRegister(), XDcfg_GetLockRegister(), XDcfg_GetMiscControlRegister(), XDcfg_GetSoftwareIdRegister(), XDcfg_GetStatusRegister(), XDcfg_InterruptHandler(), XDcfg_IntrDisable(), XDcfg_IntrEnable(), XDcfg_IntrGetEnabled(), XDcfg_IntrGetStatus(), XDcfg_IsDmaBusy(), XDcfg_ResetHw(), XDcfg_SetControlRegister(), XDcfg_SetMiscControlRegister(), XDcfg_Transfer(), XDcfgInterruptExample(), and XDcfgPolledExample().

#define XDCFG_ROM_SHADOW_OFFSET 0x28

DMA ROM Shadow Register.

Referenced by XDcfg_SetRomShadowRegister().

#define XDcfg_SelectIcapInterface | ( |  | InstancePtr | ) |

Value:
XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
& ( ~XDCFG_CTRL_PCAP_PR_MASK)))
XDcfg_ReadReg
#define XDcfg_ReadReg(BaseAddr, RegOffset)
Read the given register.
Definition: xdevcfg_hw.h:432
XDCFG_CTRL_PCAP_PR_MASK
#define XDCFG_CTRL_PCAP_PR_MASK
Enable PCAP for PR.
Definition: xdevcfg_hw.h:86
XDCFG_CTRL_OFFSET
#define XDCFG_CTRL_OFFSET
Control Register.
Definition: xdevcfg_hw.h:53
XDcfg_WriteReg
#define XDcfg_WriteReg(BaseAddr, RegOffset, Data)
Write to the given register.
Definition: xdevcfg_hw.h:450

Selects ICAP interface for reconfiguration after the initial configuration of the PL.

Parameters

  InstancePtr | is a pointer to the instance of XDcfg driver.

Returns
  None.

Note
  C-style signature: void XDcfg_SelectIcapInterface(XDcfg* InstancePtr)

#define XDcfg_SelectPcapInterface | ( |  | InstancePtr | ) |

Value:
XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
| XDCFG_CTRL_PCAP_PR_MASK))
XDcfg_ReadReg
#define XDcfg_ReadReg(BaseAddr, RegOffset)
Read the given register.
Definition: xdevcfg_hw.h:432
XDCFG_CTRL_PCAP_PR_MASK
#define XDCFG_CTRL_PCAP_PR_MASK
Enable PCAP for PR.
Definition: xdevcfg_hw.h:86
XDCFG_CTRL_OFFSET
#define XDCFG_CTRL_OFFSET
Control Register.
Definition: xdevcfg_hw.h:53
XDcfg_WriteReg
#define XDcfg_WriteReg(BaseAddr, RegOffset, Data)
Write to the given register.
Definition: xdevcfg_hw.h:450

Selects PCAP interface for reconfiguration after the initial configuration of the PL.

Parameters

  InstancePtr | is a pointer to the instance of XDcfg driver.

Returns
  None.

Note
  C-style signature: void XDcfg_SelectPcapInterface(XDcfg* InstancePtr)

#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000

DMA command Queue empty.

#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000

DMA command Queue full.

Referenced by XDcfg_GetConfigReg(), XDcfg_IsDmaBusy(), XDcfgInterruptExample(), and XDcfgPolledExample().

#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000

Number of completed DMA transfers.

#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008

BBRAM key disable.

#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002

EFuse JTAG Disable status.

#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004

Efuse Security Enable Status.

#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040

Illegal APB access.

#define XDCFG_STATUS_OFFSET 0x14

Status Register.

Referenced by XDcfg_GetConfigReg(), XDcfg_GetStatusRegister(), XDcfg_IsDmaBusy(), XDcfg_SetStatusRegister(), XDcfg_Transfer(), XDcfgInterruptExample(), and XDcfgPolledExample().

#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010

FPGA Init Status.

Referenced by XDcfg_Transfer().

#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020

PL config reset status.

#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400

First PL config done.

#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200

Global power down.

#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100

Tri-state IO during config.

#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800

Tri-state IO during HIZ.

#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000

Rx FIFO level.

#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080

Secure Reset POR Status.

#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000

Tx FIFO level.

#define XDCFG_SW_ID_OFFSET 0x30

Software ID Register.

Referenced by XDcfg_GetSoftwareIdRegister().

#define XDcfg_Unlock | ( |  | InstancePtr | ) |

Value:
XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \
XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
XDCFG_UNLOCK_OFFSET
#define XDCFG_UNLOCK_OFFSET
Unlock Register.
Definition: xdevcfg_hw.h:66
XDCFG_UNLOCK_DATA
#define XDCFG_UNLOCK_DATA
First APB access data.
Definition: xdevcfg_hw.h:406
XDcfg_WriteReg
#define XDcfg_WriteReg(BaseAddr, RegOffset, Data)
Write to the given register.
Definition: xdevcfg_hw.h:450

Unlock the Device Config Interface block.

Parameters

  InstancePtr | is a pointer to the instance of XDcfg driver.

Returns
  None.

Note
  C-style signature: void XDcfg_Unlock(XDcfg* InstancePtr)

Referenced by XDcfg_CfgInitialize().

#define XDCFG_UNLOCK_DATA 0x757BDF0D

First APB access data.

#define XDCFG_UNLOCK_OFFSET 0x34

Unlock Register.

#define XDcfg_WriteReg | ( |  | BaseAddr,
|  |  | RegOffset,
|  |  | Data
| ) |  | Xil_Out32((BaseAddr) + (RegOffset), (Data))

Write to the given register.

Parameters

  BaseAddr | is the base address of the device
  RegOffset | is the register offset to be written
  Data | is the 32-bit value to write to the register

Returns
  None.

Note
  C-style signature: void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)

Referenced by XDcfg_ClearControlRegister(), XDcfg_DisablePCAP(), XDcfg_EnablePCAP(), XDcfg_InitiateDma(), XDcfg_InterruptHandler(), XDcfg_IntrClear(), XDcfg_IntrDisable(), XDcfg_IntrEnable(), XDcfg_ResetHw(), XDcfg_SetConfigRegister(), XDcfg_SetControlRegister(), XDcfg_SetLockRegister(), XDcfg_SetMiscControlRegister(), XDcfg_SetRomShadowRegister(), XDcfg_SetStatusRegister(), and XDcfg_Transfer().

## Typedef Documentation

typedef void(* XDcfg_IntrHandler)(void *CallBackRef, u32 Status)

The handler data type allows the user to define a callback function to respond to interrupt events in the system.

This function is executed in interrupt context, so amount of processing should be minimized.

Parameters

  CallBackRef | is the callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. Its type is unimportant to the driver component, so it is a void pointer.
  Status | is the Interrupt status of the XDcfg device.

## Function Documentation

int XDcfg_CfgInitialize | ( | XDcfg * | InstancePtr,
|  | XDcfg_Config * | ConfigPtr,
|  | u32 | EffectiveAddress
| ) |  |

Initialize the Device Config Interface driver.

This function must be called before other functions of the driver are called.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.
  ConfigPtr | is the config structure.
  EffectiveAddress | is the base address for the device. It could be a virtual address if address translation is supported in the system, otherwise it is the physical address.

Returns
  - XST_SUCCESS if initialization was successful.
  - XST_DEVICE_IS_STARTED if the device has already been started.

Note
  The very first APB access to the Device Configuration Interface block needs to be a write to the UNLOCK register with the value of 0x757BDF0D. This step is to be done once after reset, any other APB access has to come after this. The APB access is considered illegal if the step is not done or if it is done incorrectly. Furthermore, if any of efuse_sec_cfg[5:0] is high, the following additional actions would be carried out. In other words, if all bits are low, the following steps are not done.
  1. AES is disabled
  2. All APB writes disabled
  3. SoC debug fully enabled

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg_Config::DeviceId, XDcfg::IsReady, XDcfg::IsStarted, and XDcfg_Unlock.

Referenced by DcfgSelfTestExample(), XDcfgInterruptExample(), XDcfgPolledExample(), and XDcfgRegReadExample().

void XDcfg_ClearControlRegister | ( | XDcfg * | InstancePtr,
|  | u32 | Mask
| ) |  |

The function Clears the specified bit positions of the Control Register.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.
  Mask | is the 32 bit value which holds the bit positions to be cleared.

Returns
  None.

Note
  None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_CTRL_OFFSET, XDcfg_ReadReg, and XDcfg_WriteReg.

void XDcfg_DisablePCAP | ( | XDcfg * | InstancePtr | ) |

The functions disables the PCAP interface by clearing the PCAP mode bit in the control register.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.

Returns
  None.

Note
  None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_CTRL_OFFSET, XDCFG_CTRL_PCAP_MODE_MASK, XDcfg_ReadReg, and XDcfg_WriteReg.

void XDcfg_EnablePCAP | ( | XDcfg * | InstancePtr | ) |

The functions enables the PCAP interface by setting the PCAP mode bit in the control register.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.

Returns
  None.

Note
  Enable FPGA programming from PCAP interface. Enabling this bit disables all the external interfaces from programming of FPGA except for ICAP. The user needs to ensure that the FPGA is programmed through either PCAP or ICAP.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_CTRL_OFFSET, XDCFG_CTRL_PCAP_MODE_MASK, XDcfg_ReadReg, and XDcfg_WriteReg.

Referenced by XDcfgInterruptExample(), and XDcfgPolledExample().

u32 XDcfg_GetConfigRegister | ( | XDcfg * | InstancePtr | ) |

The function reads the contents of the Configuration Register with the given value.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.

Returns
  A 32-bit value representing the contents of the Config Register. Use the XDCFG_CFG_*_MASK constants defined in xdevcfg_hw.h to interpret the returned value.

Note
  None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_CFG_OFFSET, and XDcfg_ReadReg.

u32 XDcfg_GetControlRegister | ( | XDcfg * | InstancePtr | ) |

The function reads the contents of the Control Register.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.

Returns
  A 32-bit value representing the contents of the Control Register. Use the XDCFG_CTRL_*_MASK constants defined in xdevcfg_hw.h to interpret the returned value.

Note
  None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_CTRL_OFFSET, and XDcfg_ReadReg.

Referenced by XDcfg_SelfTest().

u32 XDcfg_GetLockRegister | ( | XDcfg * | InstancePtr | ) |

The function reads the contents of the Lock Register.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.

Returns
  A 32-bit value representing the contents of the Lock Register. Use the XDCFG_CR_*_MASK constants defined in xdevcfg_hw.h to interpret the returned value.

Note
  None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_LOCK_OFFSET, and XDcfg_ReadReg.

u32 XDcfg_GetMiscControlRegister | ( | XDcfg * | InstancePtr | ) |

The function reads the contents of the Miscellaneous Control Register.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.

Returns
  32 Bit boot software ID.

Note
  This register is locked for write once the system enters usermode. Hence API to reading the register only is provided.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_MCTRL_OFFSET, and XDcfg_ReadReg.

u32 XDcfg_GetSoftwareIdRegister | ( | XDcfg * | InstancePtr | ) |

The function reads the contents of the Software ID Register.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.

Returns
  32 Bit boot software ID.

Note
  This register is locked for write once the system enters usermode. Hence API for reading the register only is provided.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDcfg_ReadReg, and XDCFG_SW_ID_OFFSET.

u32 XDcfg_GetStatusRegister | ( | XDcfg * | InstancePtr | ) |

The function reads the contents of the Status Register.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.

Returns
  A 32-bit value representing the contents of the Status Register. Use the XDCFG_STATUS_*_MASK constants defined in xdevcfg_hw.h to interpret the returned value.

Note
  None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDcfg_ReadReg, and XDCFG_STATUS_OFFSET.

void XDcfg_InitiateDma | ( | XDcfg * | InstancePtr,
|  | u32 | SourcePtr,
|  | u32 | DestPtr,
|  | u32 | SrcWordLength,
|  | u32 | DestWordLength
| ) |  |

This function initiates the DMA transfer.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.
  SourcePtr | contains a pointer to the source memory where the data is to be transferred from.
  SrcWordLength | is the number of words (32 bit) to be transferred for the source transfer.
  DestPtr | contains a pointer to the destination memory where the data is to be transferred to.
  DestWordLength | is the number of words (32 bit) to be transferred for the Destination transfer.

Returns
  None.

Note
  It is the responsibility of the caller function to ensure that correct values are passed to this function.

          The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination)

  address when equal to 2�b01 indicates the last DMA command of an overall transfer.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDCFG_DMA_DEST_ADDR_OFFSET, XDCFG_DMA_DEST_LEN_OFFSET, XDCFG_DMA_SRC_ADDR_OFFSET, XDCFG_DMA_SRC_LEN_OFFSET, and XDcfg_WriteReg.

Referenced by XDcfg_GetConfigReg(), and XDcfg_Transfer().

void XDcfg_InterruptHandler | ( | XDcfg * | InstancePtr | ) |

The interrupt handler for the Device Config Interface.

Events are signaled to upper layer for proper handling.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.

Returns
  None.

Note
  None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_INT_STS_OFFSET, XDcfg_ReadReg, and XDcfg_WriteReg.

Referenced by XDcfgInterruptExample().

void XDcfg_IntrClear | ( | XDcfg * | InstancePtr,
|  | u32 | Mask
| ) |  |

This function clears the specified interrupts in the Interrupt Status Register.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.
  Mask | is the bit-mask of the interrupts to be cleared. Bit positions of 1 will be cleared. Bit positions of 0 will not change the previous interrupt status. This mask is formed by OR'ing XDCFG_INT_* bits which are defined in xdevcfg_hw.h.

Returns
  None.

Note
  None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_INT_STS_OFFSET, and XDcfg_WriteReg.

Referenced by XDcfg_GetConfigReg(), XDcfgInterruptExample(), and XDcfgPolledExample().

void XDcfg_IntrDisable | ( | XDcfg * | InstancePtr,
|  | u32 | Mask
| ) |  |

This function disables the specified interrupts in the device.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.
  Mask | is the bit-mask of the interrupts to be disabled. Bit positions of 1 will be disabled. Bit positions of 0 will keep the previous setting. This mask is formed by OR'ing XDCFG_INT_* bits defined in xdevcfg_hw.h.

Returns
  None.

Note
  None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_INT_MASK_OFFSET, XDcfg_ReadReg, and XDcfg_WriteReg.

Referenced by XDcfgInterruptExample().

void XDcfg_IntrEnable | ( | XDcfg * | InstancePtr,
|  | u32 | Mask
| ) |  |

This function enables the specified interrupts in the device.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.
  Mask | is the bit-mask of the interrupts to be enabled. Bit positions of 1 will be enabled. Bit positions of 0 will keep the previous setting. This mask is formed by OR'ing XDCFG_INT_* bits defined in xdevcfg_hw.h.

Returns
  None.

Note
  None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_INT_MASK_OFFSET, XDcfg_ReadReg, and XDcfg_WriteReg.

Referenced by XDcfgInterruptExample().

u32 XDcfg_IntrGetEnabled | ( | XDcfg * | InstancePtr | ) |

This function returns the enabled interrupts read from the Interrupt Mask Register.

Use the XDCFG_INT_* constants defined in xdevcfg_hw.h to interpret the returned value.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.

Returns
  A 32-bit value representing the contents of the IMR.

Note
  None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_INT_MASK_OFFSET, and XDcfg_ReadReg.

u32 XDcfg_IntrGetStatus | ( | XDcfg * | InstancePtr | ) |

This function returns the interrupt status read from Interrupt Status Register.

Use the XDCFG_INT_* constants defined in xdevcfg_hw.h to interpret the returned value.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.

Returns
  A 32-bit value representing the contents of the Interrupt Status register.

Note
  None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_INT_STS_OFFSET, and XDcfg_ReadReg.

Referenced by XDcfg_GetConfigReg(), XDcfgInterruptExample(), and XDcfgPolledExample().

u32 XDcfg_IsDmaBusy | ( | XDcfg * | InstancePtr | ) |

This function checks if DMA command queue is full.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.

Returns
  XST_SUCCESS is the DMA is busy XST_FAILURE if the DMA is idle

Note
  The DMA queue has a depth of two.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDcfg_ReadReg, XDCFG_STATUS_DMA_CMD_Q_F_MASK, and XDCFG_STATUS_OFFSET.

Referenced by XDcfg_Transfer().

XDcfg_Config * XDcfg_LookupConfig | ( | u16 | DeviceId | ) |

Lookup the device configuration based on the unique device ID.

The table contains the configuration info for each device in the system.

Parameters

  DeviceId | is the unique device ID of the device being looked up.

Returns
  A pointer to the configuration table entry corresponding to the given device ID, or NULL if no match is found.

Note
  None.

References XDcfg_ConfigTable.

Referenced by DcfgSelfTestExample(), XDcfgInterruptExample(), XDcfgPolledExample(), and XDcfgRegReadExample().

void XDcfg_ResetHw | ( | u32 | BaseAddr | ) |

This function perform the reset sequence to the given devcfg interface by configuring the appropriate control bits in the devcfg specifc registers the devcfg reset squence involves the following steps Disable all the interuupts Clear the status Update relevant config registers with reset values Disbale the looopback mode and pcap rate enable.

Parameters

  BaseAddress | of the interface

Returns
  N/A

Note
  This function will not modify the slcr registers that are relavant for devcfg controller

References XDCFG_CFG_OFFSET, XDCFG_CONFIG_RESET_VALUE, XDCFG_CTRL_OFFSET, XDCFG_CTRL_PCAP_RATE_EN_MASK, XDCFG_DMA_DEST_ADDR_OFFSET, XDCFG_DMA_DEST_LEN_OFFSET, XDCFG_DMA_SRC_ADDR_OFFSET, XDCFG_DMA_SRC_LEN_OFFSET, XDCFG_INT_MASK_OFFSET, XDCFG_INT_STS_OFFSET, XDCFG_MCTRL_OFFSET, XDCFG_MCTRL_PCAP_LPBK_MASK, XDcfg_ReadReg, and XDcfg_WriteReg.

int XDcfg_SelfTest | ( | XDcfg * | InstancePtr | ) |

Run a self-test on the Device Configuration Interface.

This test does a control register write and reads back the same value.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.

Returns
  - XST_SUCCESS if self-test was successful.
  - XST_FAILURE if fails.

Note
  None.

References XDcfg::IsReady, XDCFG_CTRL_NIDEN_MASK, XDcfg_GetControlRegister(), and XDcfg_SetControlRegister().

Referenced by DcfgSelfTestExample(), XDcfgInterruptExample(), XDcfgPolledExample(), and XDcfgRegReadExample().

void XDcfg_SetConfigRegister | ( | XDcfg * | InstancePtr,
|  | u32 | Data
| ) |  |

The function sets the contents of the Configuration Register with the given value.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.
  Data | is the 32 bit data to be written to the Register.

Returns
  None.

Note
  None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_CFG_OFFSET, and XDcfg_WriteReg.

void XDcfg_SetControlRegister | ( | XDcfg * | InstancePtr,
|  | u32 | Mask
| ) |  |

The function sets the contents of the Control Register.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.
  Mask | is the 32 bit mask data to be written to the Register. The mask definitions are defined in the xdevcfg_hw.h file.

Returns
  None.

Note
  None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_CTRL_OFFSET, XDcfg_ReadReg, and XDcfg_WriteReg.

Referenced by XDcfg_SelfTest(), XDcfg_Transfer(), XDcfgInterruptExample(), and XDcfgPolledExample().

void XDcfg_SetHandler | ( | XDcfg * | InstancePtr,
|  | void * | CallBackFunc,
|  | void * | CallBackRef
| ) |  |

This function sets the handler that will be called when an event (interrupt) occurs that needs application's attention.

Parameters

  InstancePtr | is a pointer to the XDcfg instance
  CallBackFunc | is the address of the callback function.
  CallBackRef | is a user data item that will be passed to the callback function when it is invoked.

Returns
  None.

Note
  None.

References XDcfg::IsReady.

Referenced by XDcfgInterruptExample().

void XDcfg_SetLockRegister | ( | XDcfg * | InstancePtr,
|  | u32 | Data
| ) |  |

The function sets the contents of the Lock Register.

These bits can only be set to a 1. They will be cleared after a Power On Reset.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.
  Data | is the 32 bit data to be written to the Register.

Returns
  None.

Note
  None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_LOCK_OFFSET, and XDcfg_WriteReg.

void XDcfg_SetMiscControlRegister | ( | XDcfg * | InstancePtr,
|  | u32 | Mask
| ) |  |

The function sets the bit mask for the feature in Miscellaneous Control Register.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.
  Mask | is the bit-mask of the feature to be set.

Returns
  None.

Note
  None

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_MCTRL_OFFSET, XDcfg_ReadReg, and XDcfg_WriteReg.

void XDcfg_SetRomShadowRegister | ( | XDcfg * | InstancePtr,
|  | u32 | Data
| ) |  |

The function sets the contents of the ROM Shadow Control Register.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.
  Data | is the 32 bit data to be written to the Register.

Returns
  None.

Note
  This register is can only be written and is used to control the RAM shadow of 32 bit 4K page ROM pages in user mode

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_ROM_SHADOW_OFFSET, and XDcfg_WriteReg.

void XDcfg_SetStatusRegister | ( | XDcfg * | InstancePtr,
|  | u32 | Data
| ) |  |

The function sets the contents of the Status Register.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.
  Data | is the 32 bit data to be written to the Register.

Returns
  None.

Note
  None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_STATUS_OFFSET, and XDcfg_WriteReg.

u32 XDcfg_Transfer | ( | XDcfg * | InstancePtr,
|  | void * | SourcePtr,
|  | u32 | SrcWordLength,
|  | void * | DestPtr,
|  | u32 | DestWordLength,
|  | u32 | TransferType
| ) |  |

This function starts the DMA transfer.

This function only starts the operation and returns before the operation may be completed. If the interrupt is enabled, an interrupt will be generated when the operation is completed, otherwise it is necessary to poll the Status register to determine when it is completed. It is the responsibility of the caller to determine when the operation is completed by handling the generated interrupt or polling the Status Register.

Parameters

  InstancePtr | is a pointer to the XDcfg instance.
  SourcePtr | contains a pointer to the source memory where the data is to be transferred from.
  SrcWordLength | is the number of words (32 bit) to be transferred for the source transfer.
  DestPtr | contains a pointer to the destination memory where the data is to be transferred to.
  DestWordLength | is the number of words (32 bit) to be transferred for the Destination transfer.
  TransferType | contains the type of PCAP transfer being requested. The definitions can be found in the xdevcfg.h file.

Returns
  - XST_SUCCESS.if DMA transfer initiated successfully
  - XST_DEVICE_BUSY if DMA is busy
  - XST_INVALID_PARAM if invalid Source / Destination address is sent or an invalid Source / Destination length is sent

Note
  It is the responsibility of the caller to ensure that the cache is flushed and invalidated both before the DMA operation is started and after the DMA operation completes if the memory pointed to is cached. The caller must also ensure that the pointers contain physical address rather than a virtual address if address translation is being used.

          The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination)

  address when equal to 2�b01 indicates the last DMA command of an overall transfer.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_CTRL_OFFSET, XDCFG_CTRL_PCAP_RATE_EN_MASK, XDcfg_InitiateDma(), XDcfg_IsDmaBusy(), XDCFG_MCTRL_OFFSET, XDCFG_MCTRL_PCAP_LPBK_MASK, XDcfg_ReadReg, XDcfg_SetControlRegister(), XDCFG_STATUS_OFFSET, XDCFG_STATUS_PCFG_INIT_MASK, and XDcfg_WriteReg.

Referenced by XDcfg_GetConfigReg(), XDcfgInterruptExample(), and XDcfgPolledExample().

## Variable Documentation

XDcfg_Config XDcfg_ConfigTable[1]

Initial value:
= {
{
XPAR_XDCFG_0_DEVICE_ID,
XPAR_XDCFG_0_BASEADDR,
}
}

This table contains configuration information for each Device Config Interface instance in the system.

Referenced by XDcfg_LookupConfig().