
/*******************************************************************
* Copyright (c) 2010-2023 Xilinx, Inc. All rights reserved.
* Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
*******************************************************************/

#include "xparameters.h"
#include "xv_frmbufrd.h"

/*
* The configuration table for devices
*/

XV_frmbufrd_Config XV_frmbufrd_ConfigTable[XPAR_XV_FRMBUFRD_NUM_INSTANCES] =
{
	{
		XPAR_V_FRMBUF_RD_0_DEVICE_ID,
		XPAR_V_FRMBUF_RD_0_S_AXI_CTRL_BASEADDR,
		XPAR_V_FRMBUF_RD_0_SAMPLES_PER_CLOCK,
		XPAR_V_FRMBUF_RD_0_MAX_COLS,
		XPAR_V_FRMBUF_RD_0_MAX_ROWS,
		XPAR_V_FRMBUF_RD_0_MAX_DATA_WIDTH,
		XPAR_V_FRMBUF_RD_0_AXIMM_DATA_WIDTH,
		XPAR_V_FRMBUF_RD_0_AXIMM_ADDR_WIDTH,
		XPAR_V_FRMBUF_RD_0_HAS_RGBX8,
		XPAR_V_FRMBUF_RD_0_HAS_YUVX8,
		XPAR_V_FRMBUF_RD_0_HAS_YUYV8,
		XPAR_V_FRMBUF_RD_0_HAS_RGBA8,
		XPAR_V_FRMBUF_RD_0_HAS_YUVA8,
		XPAR_V_FRMBUF_RD_0_HAS_RGBX10,
		XPAR_V_FRMBUF_RD_0_HAS_YUVX10,
		XPAR_V_FRMBUF_RD_0_HAS_Y_UV8,
		XPAR_V_FRMBUF_RD_0_HAS_Y_UV8_420,
		XPAR_V_FRMBUF_RD_0_HAS_RGB8,
		XPAR_V_FRMBUF_RD_0_HAS_YUV8,
		XPAR_V_FRMBUF_RD_0_HAS_Y_UV10,
		XPAR_V_FRMBUF_RD_0_HAS_Y_UV10_420,
		XPAR_V_FRMBUF_RD_0_HAS_Y8,
		XPAR_V_FRMBUF_RD_0_HAS_Y10,
		XPAR_V_FRMBUF_RD_0_HAS_BGRA8,
		XPAR_V_FRMBUF_RD_0_HAS_BGRX8,
		XPAR_V_FRMBUF_RD_0_HAS_UYVY8,
		XPAR_V_FRMBUF_RD_0_HAS_BGR8,
		XPAR_V_FRMBUF_RD_0_HAS_RGBX12,
		XPAR_V_FRMBUF_RD_0_HAS_RGB16,
		XPAR_V_FRMBUF_RD_0_HAS_YUVX12,
		XPAR_V_FRMBUF_RD_0_HAS_Y_UV12,
		XPAR_V_FRMBUF_RD_0_HAS_Y_UV12_420,
		XPAR_V_FRMBUF_RD_0_HAS_Y12,
		XPAR_V_FRMBUF_RD_0_HAS_YUV16,
		XPAR_V_FRMBUF_RD_0_HAS_Y_UV16,
		XPAR_V_FRMBUF_RD_0_HAS_Y_UV16_420,
		XPAR_V_FRMBUF_RD_0_HAS_Y16,
		XPAR_V_FRMBUF_RD_0_HAS_Y_U_V8,
		XPAR_V_FRMBUF_RD_0_HAS_Y_U_V10,
		XPAR_V_FRMBUF_RD_0_HAS_Y_U_V8_420,
		XPAR_V_FRMBUF_RD_0_HAS_INTERLACED
	}
};
