| i3c Vitis Drivers API Documentation

- Overview
- Data Structures
- APIs
- File List
- Examples

- All
- Functions
- Variables
- Macros

- d
- h
- i
- m
- x

Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

### - d -

- Dynamic_Addr : xi3c_daa_example.c

### - h -

- Handler() : xi3c_intr_example.c , xi3c_slave_intr_example.c

### - i -

- I3cMasterDaaExample() : xi3c_daa_example.c
- I3cMasterIntrExample() : xi3c_intr_example.c
- I3cMasterPolledExample() : xi3c_polled_example.c
- I3cSlaveIntrExample() : xi3c_slave_intr_example.c
- I3cSlavePolledExample() : xi3c_slave_polled_example.c

### - m -

- main() : xi3c_daa_example.c , xi3c_slave_polled_example.c , xi3c_slave_intr_example.c , xi3c_polled_example.c , xi3c_intr_example.c

### - x -

- XI3C_ADDRESS_OFFSET : xi3c_hw.h
- XI3C_ALL_FIFOS_RESET_MASK : xi3c_hw.h
- XI3C_ALL_INTR_MASK : xi3c_hw.h
- XI3C_BASEADDR : xi3c_hw.h
- XI3C_BUS_IDLE_OFFSET : xi3c_hw.h
- XI3C_BusInit() : xi3c.c
- XI3c_CfgInitialize() : xi3c.c
- XI3c_ClearGrpAddr : xi3c_hw.h
- XI3C_CMD_FIFO_OFFSET : xi3c_hw.h
- XI3C_CMD_FIFO_RESET_MASK : xi3c_hw.h
- XI3c_CmdFifoLevel : xi3c_hw.h
- XI3C_CON_RD_BYTE_COUNT : xi3c_hw.h
- XI3c_ConfigIbi() : xi3c.c
- XI3c_ConfigTable : xi3c_g.c
- XI3C_CORE_PATCH_REVISION_MASK : xi3c_hw.h
- XI3C_CORE_REVISION_NUM_MASK : xi3c_hw.h
- XI3C_CORE_REVISION_NUM_SHIFT : xi3c_hw.h
- XI3C_CORE_VERSION_MAJOR_MASK : xi3c_hw.h
- XI3C_CORE_VERSION_MINOR_MASK : xi3c_hw.h
- XI3C_CR_ABORT_MASK : xi3c_hw.h
- XI3C_CR_ACCEPT_CTRL_ROLE_REQ : xi3c_hw.h
- XI3C_CR_EN_MASK : xi3c_hw.h
- XI3C_CR_HJ_MASK : xi3c_hw.h
- XI3C_CR_IBI_MASK : xi3c_hw.h
- XI3C_CR_OFFSET : xi3c_hw.h
- XI3C_CR_RESUME_MASK : xi3c_hw.h
- XI3c_DisableAllFEInterrupts : xi3c_hw.h
- XI3c_DisableAllREInterrupts : xi3c_hw.h
- XI3c_DisableFEInterrupts : xi3c_hw.h
- XI3c_DisableREInterrupts : xi3c_hw.h
- XI3c_DynaAddrAssign() : xi3c.c
- XI3c_EnableFEInterrupts : xi3c_hw.h
- XI3c_EnableREInterrupts : xi3c_hw.h
- XI3C_EVENT : xi3c_hw.h
- XI3C_FIFO_LVL_STATUS_1_OFFSET : xi3c_hw.h
- XI3C_FIFO_LVL_STATUS_OFFSET : xi3c_hw.h
- XI3c_FillCmdFifo() : xi3c.c
- XI3c_FillSlaveSendCount : xi3c_hw.h
- XI3C_GETCAPS_REG0 : xi3c_hw.h
- XI3C_GETCAPS_REG1 : xi3c_hw.h
- XI3c_GetMRL : xi3c_hw.h
- XI3c_GetMWL : xi3c_hw.h
- XI3C_GETMXDS : xi3c_hw.h
- XI3C_GETSTATUS : xi3c_hw.h
- XI3C_HW_H_ : xi3c_hw.h
- XI3C_INTERNAL_REVISION_MASK : xi3c_hw.h
- XI3C_INTR_BUS_BUSY_MASK : xi3c_hw.h
- XI3C_INTR_CLK_STALL_MASK : xi3c_hw.h
- XI3C_INTR_CMD_FIFO_NOT_EMPTY_MASK : xi3c_hw.h
- XI3C_INTR_CMD_FULL_MASK : xi3c_hw.h
- XI3C_INTR_CTRL_ROLE_REQUEST_MASK : xi3c_hw.h
- XI3C_INTR_ERROR_TYPE_CE3_MASK : xi3c_hw.h
- XI3C_INTR_FE_OFFSET : xi3c_hw.h
- XI3C_INTR_HJ_MASK : xi3c_hw.h
- XI3C_INTR_IBI_MASK : xi3c_hw.h
- XI3C_INTR_RD_FIFO_ALMOST_FULL_MASK : xi3c_hw.h
- XI3C_INTR_RD_FIFO_NOT_EMPTY_MASK : xi3c_hw.h
- XI3C_INTR_RD_FULL_MASK : xi3c_hw.h
- XI3C_INTR_RE_OFFSET : xi3c_hw.h
- XI3C_INTR_RESP_FULL_MASK : xi3c_hw.h
- XI3C_INTR_RESP_NOT_EMPTY_MASK : xi3c_hw.h
- XI3C_INTR_RETURN_ROLE_REQ_ACK_MASK : xi3c_hw.h
- XI3C_INTR_STATUS_OFFSET : xi3c_hw.h
- XI3C_INTR_WR_FIFO_ALMOST_FULL_MASK : xi3c_hw.h
- XI3C_INTR_WR_FIFO_NOT_EMPTY_MASK : xi3c_hw.h
- XI3C_MWL_MRL : xi3c_hw.h
- XI3C_OD_SCL_HIGH_TIME_OFFSET : xi3c_hw.h
- XI3C_OD_SCL_LOW_TIME_OFFSET : xi3c_hw.h
- XI3C_RD_FIFO_OFFSET : xi3c_hw.h
- XI3C_RD_FIFO_RESET_MASK : xi3c_hw.h
- XI3c_RdFifoLevel : xi3c_hw.h
- XI3c_ReadReg : xi3c_hw.h
- XI3c_ReadRxFifo() : xi3c.c
- XI3C_RESET_OFFSET : xi3c_hw.h
- XI3C_RESP_FIFO_RESET_MASK : xi3c_hw.h
- XI3C_RESP_STATUS_FIFO_OFFSET : xi3c_hw.h
- XI3c_RespFifoLevel : xi3c_hw.h
- XI3c_RespFifoNotEmpty : xi3c_hw.h
- XI3c_RxFifoNotEmpty : xi3c_hw.h
- XI3C_SCL_HIGH_TIME_OFFSET : xi3c_hw.h
- XI3C_SCL_LOW_TIME_OFFSET : xi3c_hw.h
- XI3C_SDA_HOLD_TIME_OFFSET : xi3c_hw.h
- XI3C_SOFT_RESET_MASK : xi3c_hw.h
- XI3C_SR_BUS_BUSY_MASK : xi3c_hw.h
- XI3C_SR_BUS_BUSY_SHIFT : xi3c_hw.h
- XI3C_SR_CLK_STALL_MASK : xi3c_hw.h
- XI3C_SR_CLK_STALL_SHIFT : xi3c_hw.h
- XI3C_SR_CMD_FIFO_NOT_EMPTY_MASK : xi3c_hw.h
- XI3C_SR_CMD_FULL_MASK : xi3c_hw.h
- XI3C_SR_CMD_FULL_SHIFT : xi3c_hw.h
- XI3C_SR_CTRL_ROLE_REQUEST_MASK : xi3c_hw.h
- XI3C_SR_ERROR_TYPE_CE3_MASK : xi3c_hw.h
- XI3C_SR_HJ_MASK : xi3c_hw.h
- XI3C_SR_IBI_MASK : xi3c_hw.h
- XI3C_SR_OFFSET : xi3c_hw.h
- XI3C_SR_RD_FIFO_ALMOST_FULL_MASK : xi3c_hw.h
- XI3C_SR_RD_FIFO_NOT_EMPTY_MASK : xi3c_hw.h
- XI3C_SR_RD_FULL_MASK : xi3c_hw.h
- XI3C_SR_RD_FULL_SHIFT : xi3c_hw.h
- XI3C_SR_RESP_FULL_MASK : xi3c_hw.h
- XI3C_SR_RESP_FULL_SHIFT : xi3c_hw.h
- XI3C_SR_RESP_NOT_EMPTY_MASK : xi3c_hw.h
- XI3C_SR_RESP_NOT_EMPTY_SHIFT : xi3c_hw.h
- XI3C_SR_RETURN_ROLE_REQ_ACK_MASK : xi3c_hw.h
- XI3C_SR_SLV_DYNC_ADDR_DONE_MASK : xi3c_hw.h
- XI3C_SR_SLV_DYNC_ADDR_DONE_SHIFT : xi3c_hw.h
- XI3C_SR_WR_FIFO_NOT_EMPTY_MASK : xi3c_hw.h
- XI3C_SR_WR_FULL_MASK : xi3c_hw.h
- XI3C_SR_WR_FULL_SHIFT : xi3c_hw.h
- XI3C_TARGET_ADDR_BCR : xi3c_hw.h
- XI3C_THD_START_OFFSET : xi3c_hw.h
- XI3C_TSU_START_OFFSET : xi3c_hw.h
- XI3C_TSU_STOP_OFFSET : xi3c_hw.h
- XI3C_VERSION_OFFSET : xi3c_hw.h
- XI3C_WR_FIFO_OFFSET : xi3c_hw.h
- XI3C_WR_FIFO_RESET_MASK : xi3c_hw.h
- XI3c_WrFifoLevel : xi3c_hw.h
- XI3c_WriteReg : xi3c_hw.h
- XI3c_WriteTxFifo() : xi3c.c