| clk_wiz Vitis Drivers API Documentation

- Overview
- Data Structures
- APIs
- File List
- Examples

Data Structures | Macros | Typedefs | Functions
Overview

## Data Structures
struct | XClk_Wiz_Config
| The configuration structure for CLK_WIZ Controller This structure passes the hardware building information to the driver. More...
struct | XClk_Wiz
| The XClk_Wiz driver instance data. More...

## Macros
#define | XCLK_WIZ_IER_ALLINTR_MASK 0x0000FFFF
| All interrupts enable mask. More...
#define | XCLK_WIZ_IER_ALLINTR_SHIFT 0
| All interrupts enable shift bits. More...
#define | XCLK_WIZ_ISR_ALLINTR_MASK 0x0000FFFF
| All interrupt status register mask. More...
#define | XCLK_WIZ_ISR_ALLINTR_SHIFT 0
| All interrupts status register shift. More...

## Typedefs
typedef void(* | XClk_Wiz_CallBack )(void *CallBackRef, u32 Mask)
| Callback type for all interrupts defined. More...

## Functions
u32 | XClk_Wiz_CfgInitialize (XClk_Wiz *InstancePtr, XClk_Wiz_Config *CfgPtr, UINTPTR EffectiveAddr)
| Initialize the XClk_Wiz instance provided by the caller based on the given Config structure. More...
void | XClk_Wiz_SetMinErr (XClk_Wiz *InstancePtr, u64 Minerr)
| Set the Minimum error that can be tolerated. More...
u32 | XClk_Wiz_SetRateHz (XClk_Wiz *InstancePtr, u64 SetRate)
| Change the frequency to the given rate in Hz. More...
s32 | XClk_Wiz_GetRate (XClk_Wiz *InstancePtr, u32 ClockId, u64 *Rate)
| Get the clock frequency for the given ClockId. More...
s32 | XClk_Wiz_SetLeafRateHz (XClk_Wiz *InstancePtr, u32 ClockId, u64 SetRate)
| Set the clock rate frequency for the given ClockId. More...
u32 | XClk_Wiz_SetRate (XClk_Wiz *InstancePtr, u64 SetRate)
| Change the frequency to the given rate. More...
u32 | XClk_Wiz_EnableClock (XClk_Wiz *InstancePtr, u32 ClockId)
| Enable Clock for the given ClockId. More...
u32 | XClk_Wiz_DisableClock (XClk_Wiz *InstancePtr, u32 ClockId)
| Disable Clock for the given ClockId. More...
u32 | XClk_Wiz_WaitForLock (XClk_Wiz *InstancePtr)
| Wait till the clocking wizard is locked to the frequency. More...
void | XClk_Wiz_SetInputRate (XClk_Wiz *InstancePtr, double Rate)
| Change the Input frequency to the given rate. More...
void | XClk_Wiz_GetInterruptSettings (XClk_Wiz *InstancePtr)
| XClk_Wiz_GetInterruptSettings will get the information from clock wizard IER and ISR Registers. More...
XClk_Wiz_Config * | XClk_Wiz_LookupConfig (u32 DeviceId)
| Look up the hardware configuration for a device instance. More...
int | XClk_Wiz_SetCallBack (XClk_Wiz *InstancePtr, u32 HandleType, void *CallBackFunc, void *CallBackRef)
| This routine installs an asynchronous callback function for the given HandlerType: More...
void | XClk_Wiz_InterruptEnable (XClk_Wiz *InstancePtr, u32 Mask)
| XClk_Wiz_InterruptEnable will enable the interrupts present in the interrupt mask passed onto the function. More...
void | XClk_Wiz_InterruptDisable (XClk_Wiz *InstancePtr, u32 Mask)
| XClk_Wiz_InterruptDisable will disable the interrupts present in the interrupt mask passed onto the function. More...
u32 | XClk_Wiz_InterruptGetEnabled (XClk_Wiz *InstancePtr)
| XClk_Wiz_InterruptGetEnabled will get the interrupt mask set (enabled) in the CLK_WIZ core. More...
u32 | XClk_Wiz_InterruptGetStatus (XClk_Wiz *InstancePtr)
| XClk_Wiz_InterruptGetStatus will get the list of interrupts pending in the Interrupt Status Register of the CLK_WIZ core. More...
void | XClk_Wiz_InterruptClear (XClk_Wiz *InstancePtr, u32 Mask)
| XClk_Wiz_InterruptClear will clear the interrupts set in the Interrupt Status Register of the CLK_WIZ core. More...
void | XClk_Wiz_IntrHandler (void *InstancePtr)
| This function is the interrupt handler for the CLK_WIZ core. More...

## Interrupt Types for setting Callbacks
#define | XCLK_WIZ_HANDLER_CLK_OUTOF_RANGE 1
#define | XCLK_WIZ_HANDLER_CLK_GLITCH 2
#define | XCLK_WIZ_HANDLER_CLK_STOP 3
#define | XCLK_WIZ_HANDLER_CLK_OTHER_ERROR 4
#define | XCLK_M_MIN 4
#define | XCLK_M_MAX 432
#define | XCLK_D_MIN 1
#define | XCLK_D_MAX 123
#define | XCLK_VCO_MIN 2160
#define | XCLK_VCO_MAX 4320
#define | XCLK_O_MIN 2
#define | XCLK_O_MAX 511
#define | XCLK_US_VCO_MAX 1600
#define | XCLK_US_VCO_MIN 800
#define | XCLK_US_M_MIN 2
#define | XCLK_US_M_MAX 128
#define | XCLK_US_D_MAX 106
#define | XCLK_US_D_MIN 1
#define | XCLK_US_O_MAX 128
#define | XCLK_US_O_MIN 1
#define | XCLK_MHZ 1000000

## Device registers
Register sets of CLK_WIZ
#define | XCLK_WIZ_STATUS_OFFSET 0x00000004
| Status Register. More...
#define | XCLK_WIZ_ISR_OFFSET 0x0000000C
| Interrupt Status Register. More...
#define | XCLK_WIZ_IER_OFFSET 0x00000010
| Interrupt Enable Register. More...
#define | XCLK_WIZ_RECONFIG_OFFSET 0x00000014
| Reconfig Register. More...
#define | XCLK_WIZ_REG1_OFFSET 0x00000330
#define | XCLK_WIZ_REG2_OFFSET 0x00000334
#define | XCLK_WIZ_REG3_OFFSET 0x00000338
#define | XCLK_WIZ_REG4_OFFSET 0x0000033C
#define | XCLK_WIZ_REG12_OFFSET 0x00000380
#define | XCLK_WIZ_REG13_OFFSET 0x00000384
#define | XCLK_WIZ_REG11_OFFSET 0x00000378
#define | XCLK_WIZ_REG14_OFFSET 0x00000398
#define | XCLK_WIZ_REG15_OFFSET 0x0000039C
#define | XCLK_WIZ_REG16_OFFSET 0x000003A0
#define | XCLK_WIZ_REG17_OFFSET 0x000003A8
#define | XCLK_WIZ_REG19_OFFSET 0x000003CC
#define | XCLK_WIZ_REG25_OFFSET 0x000003F0
#define | XCLK_WIZ_REG26_OFFSET 0x000003FC
#define | XCLK_WIZ_ZYNQMP_REG0_OFFSET 0x00000200
#define | XCLK_WIZ_ZYNQMP_REG2_OFFSET 0x00000208
#define | XCLK_WIZ_REG0_FBMULT_SHIFT 8
#define | XCLK_WIZ_REG0_FBMULT_WIDTH 8
#define | XCLK_WIZ_REG0_FBMULT_MASK 0xFF00
#define | XCLK_WIZ_REG0_DIV_MASK 0xFF
#define | XCLK_WIZ_REG0_DIV_WIDTH 8
#define | XCLK_WIZ_REG2_DIV_MASK 0xFF
#define | XCLK_WIZ_REG1_EDGE_SHIFT 8
| Shift bits for Edge. More...
#define | XCLK_WIZ_REG1_EDGE_SHIFT 8
| Shift bits for Edge. More...
#define | XCLK_WIZ_REG1_EDGE_MASK 0x100
#define | XCLK_WIZ_CLKFBOUT_L_MASK 0xFF
#define | XCLK_WIZ_CLKFBOUT_H_MASK 0xFF00
#define | XCLK_WIZ_CLKFBOUT_H_SHIFT 8
#define | XCLK_WIZ_EDGE_MASK (1 << 10) /** Edge */
#define | XCLK_WIZ_P5EN_MASK (1 << 8) /** p5en */
#define | XCLK_WIZ_LOCK 1 /** Lock */
#define | XCLK_WIZ_REG3_PREDIV2 (1 << 11)
| Prediv2 3. More...
#define | XCLK_WIZ_REG3_USED (1 << 12)
| Prediv2 3. More...
#define | XCLK_WIZ_REG3_MX (1 << 9)
| MX. More...
#define | XCLK_WIZ_REG1_PREDIV2 (1 << 12)
| Prediv2 3. More...
#define | XCLK_WIZ_REG1_EN (1 << 9)
| FBout enable. More...
#define | XCLK_WIZ_REG1_MX (1 << 10)
| MX 3. More...
#define | XCLK_WIZ_RECONFIG_LOAD 1
#define | XCLK_WIZ_RECONFIG_SADDR 2
#define | XCLK_WIZ_CLKOUT0_PREDIV2_SHIFT 11
| Shift bits for Prediv2. More...
#define | XCLK_WIZ_CLKOUT0_MX_SHIFT 9
| Shift bits for MUX. More...
#define | XCLK_WIZ_CLKOUT0_P5EN_SHIFT 13
| Shift bits for P5EN. More...
#define | XCLK_WIZ_CLKOUT0_P5FEDGE_SHIFT 15
| Shift bits for P5EDGE. More...
#define | XCLK_WIZ_CLKOUT0_P5FEDGE_MASK (1 << 15)
| Mask for P5EDGE. More...
#define | XCLK_WIZ_REG12_EDGE_SHIFT 10
| Shift bits for Edge. More...

## Bitmasks and offsets of XCLK_WIZ_ISR_OFFSET register
This register is used to display interrupt status register
#define | XCLK_WIZ_ISR_CLK3_STOP_MASK 0x00008000
| User clock 3 stopped. More...
#define | XCLK_WIZ_ISR_CLK2_STOP_MASK 0x00004000
| User clock 2 stopped. More...
#define | XCLK_WIZ_ISR_CLK1_STOP_MASK 0x00002000
| User clock 1 stopped. More...
#define | XCLK_WIZ_ISR_CLK0_STOP_MASK 0x00001000
| User clock 0 stopped. More...
#define | XCLK_WIZ_ISR_CLK3_GLITCH_MASK 0x00000800
| User clock 3 has glitch. More...
#define | XCLK_WIZ_ISR_CLK2_GLITCH_MASK 0x00000400
| User clock 2 has glitch. More...
#define | XCLK_WIZ_ISR_CLK1_GLITCH_MASK 0x00000200
| User clock 1 has glitch. More...
#define | XCLK_WIZ_ISR_CLK0_GLITCH_MASK 0x00000100
| User clock 0 has glitch. More...
#define | XCLK_WIZ_ISR_CLK3_MINFREQ_MASK 0x00000080
| User clock 3 is less than specification. More...
#define | XCLK_WIZ_ISR_CLK2_MINFREQ_MASK 0x00000040
| User clock 2 is less than specification. More...
#define | XCLK_WIZ_ISR_CLK1_MINFREQ_MASK 0x00000020
| User clock 1 is less than specification. More...
#define | XCLK_WIZ_ISR_CLK0_MINFREQ_MASK 0x00000010
| User clock 0 is less than specification. More...
#define | XCLK_WIZ_ISR_CLK3_MAXFREQ_MASK 0x00000008
| User clock 3 is max than specification. More...
#define | XCLK_WIZ_ISR_CLK2_MAXFREQ_MASK 0x00000004
| User clock 2 is max than specification. More...
#define | XCLK_WIZ_ISR_CLK1_MAXFREQ_MASK 0x00000002
| User clock 1 is max than specification. More...
#define | XCLK_WIZ_ISR_CLK0_MAXFREQ_MASK 0x00000001
| User clock 0 is max than specification. More...
#define | XCLK_WIZ_ISR_CLKALL_STOP_MASK 0x0000F000
| User clock[0-3] has stopped. More...
#define | XCLK_WIZ_ISR_CLKALL_GLITCH_MASK 0x00000F00
| User clock[0-3] has glitch. More...
#define | XCLK_WIZ_ISR_CLKALL_MINFREQ_MASK 0x000000F0
| User clock[0-3] is min than specification. More...
#define | XCLK_WIZ_ISR_CLKALL_MAXFREQ_MASK 0x0000000F
| User clock[0-3] is max than specification. More...
#define | XCLK_WIZ_ISR_CLK3_STOP_SHIFT 15
| Shift bits for User clock 3 stop. More...
#define | XCLK_WIZ_ISR_CLK2_STOP_SHIFT 14
| Shift bits for User clock 2 stop. More...
#define | XCLK_WIZ_ISR_CLK1_STOP_SHIFT 13
| Shift bits for User clock 1 stop. More...
#define | XCLK_WIZ_ISR_CLK0_STOP_SHIFT 12
| Shift bits for User clock 0 stop. More...
#define | XCLK_WIZ_ISR_CLK3_GLITCH_SHIFT 11
| Shift bits for User clock 3 glitch. More...
#define | XCLK_WIZ_ISR_CLK2_GLITCH_SHIFT 10
| Shift bits for User clock 2 glitch. More...
#define | XCLK_WIZ_ISR_CLK1_GLITCH_SHIFT 9
| Shift bits for User clock 1 glitch. More...
#define | XCLK_WIZ_ISR_CLK0_GLITCH_SHIFT 8
| Shift bits for User clock 0 glitch. More...
#define | XCLK_WIZ_ISR_CLK3_MINFREQ_SHIFT 7
| Shift bits for User clock 3 less. More...
#define | XCLK_WIZ_ISR_CLK2_MINFREQ_SHIFT 6
| Shift bits for User clock 2 less. More...
#define | XCLK_WIZ_ISR_CLK1_MINFREQ_SHIFT 5
| Shift bits for User clock 1 less. More...
#define | XCLK_WIZ_ISR_CLK0_MINFREQ_SHIFT 4
| Shift bits for User clock 0 less. More...
#define | XCLK_WIZ_ISR_CLK3_MAXFREQ_SHIFT 3
| Shift bits for User clock 3 max. More...
#define | XCLK_WIZ_ISR_CLK2_MAXFREQ_SHIFT 2
| Shift bits for User clock 2 max. More...
#define | XCLK_WIZ_ISR_CLK1_MAXFREQ_SHIFT 1
| Shift bits for User clock 1 max. More...
#define | XCLK_WIZ_ISR_CLK0_MAXFREQ_SHIFT 0
| Shift bits for User clock 0 max. More...

## Bitmasks and offsets of XCLK_WIZ_IER_OFFSET register
This register is used to display interrupt status register
#define | XCLK_WIZ_IER_CLK3_STOP_MASK 0x00008000
| User clock 3 stopped. More...
#define | XCLK_WIZ_IER_CLK2_STOP_MASK 0x00004000
| User clock 2 stopped. More...
#define | XCLK_WIZ_IER_CLK1_STOP_MASK 0x00002000
| User clock 1 stopped. More...
#define | XCLK_WIZ_IER_CLK0_STOP_MASK 0x00001000
| User clock 0 stopped. More...
#define | XCLK_WIZ_IER_CLK3_GLITCH_MASK 0x00000800
| User clock 3 has glitch. More...
#define | XCLK_WIZ_IER_CLK2_GLITCH_MASK 0x00000400
| User clock 2 has glitch. More...
#define | XCLK_WIZ_IER_CLK1_GLITCH_MASK 0x00000200
| User clock 1 has glitch. More...
#define | XCLK_WIZ_IER_CLK0_GLITCH_MASK 0x00000100
| User clock 0 has glitch. More...
#define | XCLK_WIZ_IER_CLK3_MINFREQ_MASK 0x00000080
| User clock 3 is less than specification. More...
#define | XCLK_WIZ_IER_CLK2_MINFREQ_MASK 0x00000040
| User clock 2 is less than specification. More...
#define | XCLK_WIZ_IER_CLK1_MINFREQ_MASK 0x00000020
| User clock 1 is less than specification. More...
#define | XCLK_WIZ_IER_CLK0_MINFREQ_MASK 0x00000010
| User clock 0 is less than specification. More...
#define | XCLK_WIZ_IER_CLK3_MAXFREQ_MASK 0x00000008
| User clock 3 is max than specification. More...
#define | XCLK_WIZ_IER_CLK2_MAXFREQ_MASK 0x00000004
| User clock 2 is max than specification. More...
#define | XCLK_WIZ_IER_CLK1_MAXFREQ_MASK 0x00000002
| User clock 1 is max than specification. More...
#define | XCLK_WIZ_IER_CLK0_MAXFREQ_MASK 0x00000001
| User clock 0 is max than specification. More...
#define | XCLK_WIZ_IER_CLK3_STOP_SHIFT 15
| Shift bits for User clock 3 stop. More...
#define | XCLK_WIZ_IER_CLK2_STOP_SHIFT 14
| Shift bits for User clock 2 stop. More...
#define | XCLK_WIZ_IER_CLK1_STOP_SHIFT 13
| Shift bits for User clock 1 stop. More...
#define | XCLK_WIZ_IER_CLK0_STOP_SHIFT 12
| Shift bits for User clock 0 stop. More...
#define | XCLK_WIZ_IER_CLK3_GLITCH_SHIFT 11
| Shift bits for User clock 3 glitch. More...
#define | XCLK_WIZ_IER_CLK2_GLITCH_SHIFT 10
| Shift bits for User clock 2 glitch. More...
#define | XCLK_WIZ_IER_CLK1_GLITCH_SHIFT 9
| Shift bits for User clock 1 glitch. More...
#define | XCLK_WIZ_IER_CLK0_GLITCH_SHIFT 8
| Shift bits for User clock 0 glitch. More...
#define | XCLK_WIZ_IER_CLK3_MINFREQ_SHIFT 7
| Shift bits for User clock 3 less. More...
#define | XCLK_WIZ_IER_CLK2_MINFREQ_SHIFT 6
| Shift bits for User clock 2 less. More...
#define | XCLK_WIZ_IER_CLK1_MINFREQ_SHIFT 5
| Shift bits for User clock 1 less. More...
#define | XCLK_WIZ_IER_CLK0_MINFREQ_SHIFT 4
| Shift bits for User clock 0 less. More...
#define | XCLK_WIZ_IER_CLK3_MAXFREQ_SHIFT 3
| Shift bits for User clock 3 max. More...
#define | XCLK_WIZ_IER_CLK2_MAXFREQ_SHIFT 2
| Shift bits for User clock 2 max. More...
#define | XCLK_WIZ_IER_CLK1_MAXFREQ_SHIFT 1
| Shift bits for User clock 1 max. More...
#define | XCLK_WIZ_IER_CLK0_MAXFREQ_SHIFT 0
| Shift bits for User clock 0 max. More...

## Macro Definition Documentation

#define XCLK_WIZ_CLKOUT0_MX_SHIFT 9

Shift bits for MUX.

#define XCLK_WIZ_CLKOUT0_P5EN_SHIFT 13

Shift bits for P5EN.

#define XCLK_WIZ_CLKOUT0_P5FEDGE_MASK (1 << 15)

Mask for P5EDGE.

Referenced by XClk_Wiz_GetRate().

#define XCLK_WIZ_CLKOUT0_P5FEDGE_SHIFT 15

Shift bits for P5EDGE.

#define XCLK_WIZ_CLKOUT0_PREDIV2_SHIFT 11

Shift bits for Prediv2.

#define XCLK_WIZ_IER_ALLINTR_MASK 0x0000FFFF

All interrupts enable mask.

Referenced by ClkWiz_IntrExample(), XClk_Wiz_GetInterruptSettings(), XClk_Wiz_InterruptClear(), XClk_Wiz_InterruptDisable(), and XClk_Wiz_InterruptEnable().

#define XCLK_WIZ_IER_ALLINTR_SHIFT 0

All interrupts enable shift bits.

Referenced by XClk_Wiz_GetInterruptSettings().

#define XCLK_WIZ_IER_CLK0_GLITCH_MASK 0x00000100

User clock 0 has glitch.

#define XCLK_WIZ_IER_CLK0_GLITCH_SHIFT 8

Shift bits for User clock 0 glitch.

#define XCLK_WIZ_IER_CLK0_MAXFREQ_MASK 0x00000001

User clock 0 is max than specification.

#define XCLK_WIZ_IER_CLK0_MAXFREQ_SHIFT 0

Shift bits for User clock 0 max.

#define XCLK_WIZ_IER_CLK0_MINFREQ_MASK 0x00000010

User clock 0 is less than specification.

#define XCLK_WIZ_IER_CLK0_MINFREQ_SHIFT 4

Shift bits for User clock 0 less.

#define XCLK_WIZ_IER_CLK0_STOP_MASK 0x00001000

User clock 0 stopped.

#define XCLK_WIZ_IER_CLK0_STOP_SHIFT 12

Shift bits for User clock 0 stop.

#define XCLK_WIZ_IER_CLK1_GLITCH_MASK 0x00000200

User clock 1 has glitch.

#define XCLK_WIZ_IER_CLK1_GLITCH_SHIFT 9

Shift bits for User clock 1 glitch.

#define XCLK_WIZ_IER_CLK1_MAXFREQ_MASK 0x00000002

User clock 1 is max than specification.

#define XCLK_WIZ_IER_CLK1_MAXFREQ_SHIFT 1

Shift bits for User clock 1 max.

#define XCLK_WIZ_IER_CLK1_MINFREQ_MASK 0x00000020

User clock 1 is less than specification.

#define XCLK_WIZ_IER_CLK1_MINFREQ_SHIFT 5

Shift bits for User clock 1 less.

#define XCLK_WIZ_IER_CLK1_STOP_MASK 0x00002000

User clock 1 stopped.

#define XCLK_WIZ_IER_CLK1_STOP_SHIFT 13

Shift bits for User clock 1 stop.

#define XCLK_WIZ_IER_CLK2_GLITCH_MASK 0x00000400

User clock 2 has glitch.

#define XCLK_WIZ_IER_CLK2_GLITCH_SHIFT 10

Shift bits for User clock 2 glitch.

#define XCLK_WIZ_IER_CLK2_MAXFREQ_MASK 0x00000004

User clock 2 is max than specification.

#define XCLK_WIZ_IER_CLK2_MAXFREQ_SHIFT 2

Shift bits for User clock 2 max.

#define XCLK_WIZ_IER_CLK2_MINFREQ_MASK 0x00000040

User clock 2 is less than specification.

#define XCLK_WIZ_IER_CLK2_MINFREQ_SHIFT 6

Shift bits for User clock 2 less.

#define XCLK_WIZ_IER_CLK2_STOP_MASK 0x00004000

User clock 2 stopped.

#define XCLK_WIZ_IER_CLK2_STOP_SHIFT 14

Shift bits for User clock 2 stop.

#define XCLK_WIZ_IER_CLK3_GLITCH_MASK 0x00000800

User clock 3 has glitch.

#define XCLK_WIZ_IER_CLK3_GLITCH_SHIFT 11

Shift bits for User clock 3 glitch.

#define XCLK_WIZ_IER_CLK3_MAXFREQ_MASK 0x00000008

User clock 3 is max than specification.

#define XCLK_WIZ_IER_CLK3_MAXFREQ_SHIFT 3

Shift bits for User clock 3 max.

#define XCLK_WIZ_IER_CLK3_MINFREQ_MASK 0x00000080

User clock 3 is less than specification.

#define XCLK_WIZ_IER_CLK3_MINFREQ_SHIFT 7

Shift bits for User clock 3 less.

#define XCLK_WIZ_IER_CLK3_STOP_MASK 0x00008000

User clock 3 stopped.

#define XCLK_WIZ_IER_CLK3_STOP_SHIFT 15

Shift bits for User clock 3 stop.

#define XCLK_WIZ_IER_OFFSET 0x00000010

Interrupt Enable Register.

Referenced by XClk_Wiz_GetInterruptSettings().

#define XCLK_WIZ_ISR_ALLINTR_MASK 0x0000FFFF

All interrupt status register mask.

Referenced by XClk_Wiz_GetInterruptSettings().

#define XCLK_WIZ_ISR_ALLINTR_SHIFT 0

All interrupts status register shift.

Referenced by XClk_Wiz_GetInterruptSettings().

#define XCLK_WIZ_ISR_CLK0_GLITCH_MASK 0x00000100

User clock 0 has glitch.

Referenced by ClkWiz_ClkGlitchEventHandler().

#define XCLK_WIZ_ISR_CLK0_GLITCH_SHIFT 8

Shift bits for User clock 0 glitch.

#define XCLK_WIZ_ISR_CLK0_MAXFREQ_MASK 0x00000001

User clock 0 is max than specification.

Referenced by ClkWiz_ClkOutOfRangeEventHandler().

#define XCLK_WIZ_ISR_CLK0_MAXFREQ_SHIFT 0

Shift bits for User clock 0 max.

#define XCLK_WIZ_ISR_CLK0_MINFREQ_MASK 0x00000010

User clock 0 is less than specification.

Referenced by ClkWiz_ClkOutOfRangeEventHandler().

#define XCLK_WIZ_ISR_CLK0_MINFREQ_SHIFT 4

Shift bits for User clock 0 less.

#define XCLK_WIZ_ISR_CLK0_STOP_MASK 0x00001000

User clock 0 stopped.

Referenced by ClkWiz_ClkStopEventHandler().

#define XCLK_WIZ_ISR_CLK0_STOP_SHIFT 12

Shift bits for User clock 0 stop.

#define XCLK_WIZ_ISR_CLK1_GLITCH_MASK 0x00000200

User clock 1 has glitch.

Referenced by ClkWiz_ClkGlitchEventHandler().

#define XCLK_WIZ_ISR_CLK1_GLITCH_SHIFT 9

Shift bits for User clock 1 glitch.

#define XCLK_WIZ_ISR_CLK1_MAXFREQ_MASK 0x00000002

User clock 1 is max than specification.

Referenced by ClkWiz_ClkOutOfRangeEventHandler().

#define XCLK_WIZ_ISR_CLK1_MAXFREQ_SHIFT 1

Shift bits for User clock 1 max.

#define XCLK_WIZ_ISR_CLK1_MINFREQ_MASK 0x00000020

User clock 1 is less than specification.

Referenced by ClkWiz_ClkOutOfRangeEventHandler().

#define XCLK_WIZ_ISR_CLK1_MINFREQ_SHIFT 5

Shift bits for User clock 1 less.

#define XCLK_WIZ_ISR_CLK1_STOP_MASK 0x00002000

User clock 1 stopped.

Referenced by ClkWiz_ClkStopEventHandler().

#define XCLK_WIZ_ISR_CLK1_STOP_SHIFT 13

Shift bits for User clock 1 stop.

#define XCLK_WIZ_ISR_CLK2_GLITCH_MASK 0x00000400

User clock 2 has glitch.

Referenced by ClkWiz_ClkGlitchEventHandler().

#define XCLK_WIZ_ISR_CLK2_GLITCH_SHIFT 10

Shift bits for User clock 2 glitch.

#define XCLK_WIZ_ISR_CLK2_MAXFREQ_MASK 0x00000004

User clock 2 is max than specification.

Referenced by ClkWiz_ClkOutOfRangeEventHandler().

#define XCLK_WIZ_ISR_CLK2_MAXFREQ_SHIFT 2

Shift bits for User clock 2 max.

#define XCLK_WIZ_ISR_CLK2_MINFREQ_MASK 0x00000040

User clock 2 is less than specification.

Referenced by ClkWiz_ClkOutOfRangeEventHandler().

#define XCLK_WIZ_ISR_CLK2_MINFREQ_SHIFT 6

Shift bits for User clock 2 less.

#define XCLK_WIZ_ISR_CLK2_STOP_MASK 0x00004000

User clock 2 stopped.

Referenced by ClkWiz_ClkStopEventHandler().

#define XCLK_WIZ_ISR_CLK2_STOP_SHIFT 14

Shift bits for User clock 2 stop.

#define XCLK_WIZ_ISR_CLK3_GLITCH_MASK 0x00000800

User clock 3 has glitch.

Referenced by ClkWiz_ClkGlitchEventHandler().

#define XCLK_WIZ_ISR_CLK3_GLITCH_SHIFT 11

Shift bits for User clock 3 glitch.

#define XCLK_WIZ_ISR_CLK3_MAXFREQ_MASK 0x00000008

User clock 3 is max than specification.

Referenced by ClkWiz_ClkOutOfRangeEventHandler().

#define XCLK_WIZ_ISR_CLK3_MAXFREQ_SHIFT 3

Shift bits for User clock 3 max.

#define XCLK_WIZ_ISR_CLK3_MINFREQ_MASK 0x00000080

User clock 3 is less than specification.

Referenced by ClkWiz_ClkOutOfRangeEventHandler().

#define XCLK_WIZ_ISR_CLK3_MINFREQ_SHIFT 7

Shift bits for User clock 3 less.

#define XCLK_WIZ_ISR_CLK3_STOP_MASK 0x00008000

User clock 3 stopped.

Referenced by ClkWiz_ClkStopEventHandler().

#define XCLK_WIZ_ISR_CLK3_STOP_SHIFT 15

Shift bits for User clock 3 stop.

#define XCLK_WIZ_ISR_CLKALL_GLITCH_MASK 0x00000F00

User clock[0-3] has glitch.

Referenced by XClk_Wiz_IntrHandler().

#define XCLK_WIZ_ISR_CLKALL_MAXFREQ_MASK 0x0000000F

User clock[0-3] is max than specification.

Referenced by XClk_Wiz_IntrHandler().

#define XCLK_WIZ_ISR_CLKALL_MINFREQ_MASK 0x000000F0

User clock[0-3] is min than specification.

Referenced by XClk_Wiz_IntrHandler().

#define XCLK_WIZ_ISR_CLKALL_STOP_MASK 0x0000F000

User clock[0-3] has stopped.

Referenced by XClk_Wiz_IntrHandler().

#define XCLK_WIZ_ISR_OFFSET 0x0000000C

Interrupt Status Register.

Referenced by XClk_Wiz_GetInterruptSettings().

#define XCLK_WIZ_RECONFIG_OFFSET 0x00000014

Reconfig Register.

Referenced by ClkWiz_Example().

#define XCLK_WIZ_REG12_EDGE_SHIFT 10

Shift bits for Edge.

#define XCLK_WIZ_REG1_EDGE_SHIFT 8

Shift bits for Edge.

#define XCLK_WIZ_REG1_EDGE_SHIFT 8

Shift bits for Edge.

#define XCLK_WIZ_REG1_EN (1 << 9)

FBout enable.

#define XCLK_WIZ_REG1_MX (1 << 10)

MX 3.

#define XCLK_WIZ_REG1_PREDIV2 (1 << 12)

Prediv2 3.

#define XCLK_WIZ_REG3_MX (1 << 9)

MX.

#define XCLK_WIZ_REG3_PREDIV2 (1 << 11)

Prediv2 3.

Referenced by XClk_Wiz_GetRate().

#define XCLK_WIZ_REG3_USED (1 << 12)

Prediv2 3.

Referenced by XClk_Wiz_DisableClock(), and XClk_Wiz_EnableClock().

#define XCLK_WIZ_STATUS_OFFSET 0x00000004

Status Register.

Referenced by ClkWiz_Example(), and XClk_Wiz_WaitForLock().

## Typedef Documentation

typedef void(* XClk_Wiz_CallBack)(void *CallBackRef, u32 Mask)

Callback type for all interrupts defined.

Parameters

  CallBackRef | is a callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked.
  Mask | is a bit mask indicating the cause of the event. For current core version, this parameter is "OR" of 0 or more XCLK_WIZ_ISR_*_MASK constants defined in xclmon_hw.h.

Returns
  None

Note
  None

## Function Documentation

u32 XClk_Wiz_CfgInitialize | ( | XClk_Wiz * | InstancePtr,
|  | XClk_Wiz_Config * | CfgPtr,
|  | UINTPTR | EffectiveAddr
| ) |  |

Initialize the XClk_Wiz instance provided by the caller based on the given Config structure.

Parameters

  InstancePtr | is the XClk_Wiz instance to operate on.
  CfgPtr | is the device configuration structure containing information about a specific CLK_WIZ.
  EffectiveAddr | is the base address of the device. If address translation is being used, then this parameter must reflect the virtual base address. Otherwise, the physical address should be used.

Returns
  - XST_SUCCESS Initialization was successful.
  - XST_FAILURE Initialization was failure.

Note
  None

References XClk_Wiz_Config::BaseAddr, XClk_Wiz::ClkGlitchCallBack, XClk_Wiz::ClkOutOfRangeCallBack, XClk_Wiz::ClkStopCallBack, XClk_Wiz::Config, XClk_Wiz::ErrorCallBack, and XClk_Wiz::IsReady.

Referenced by ClkWiz_Example(), and ClkWiz_IntrExample().

u32 XClk_Wiz_DisableClock | ( | XClk_Wiz * | InstancePtr,
|  | u32 | ClockId
| ) |  |

Disable Clock for the given ClockId.

Parameters

  InstancePtr | is the XClk_Wiz instance to operate on.
  ClockId | is the output clock.

Returns
  - XST_SUCCESS Initialization was successful.
  - XST_FAILURE Initialization was failure.

References XClk_Wiz_Config::BaseAddr, XClk_Wiz::Config, XClk_Wiz::IsReady, and XCLK_WIZ_REG3_USED.

u32 XClk_Wiz_EnableClock | ( | XClk_Wiz * | InstancePtr,
|  | u32 | ClockId
| ) |  |

Enable Clock for the given ClockId.

Parameters

  InstancePtr | is the XClk_Wiz instance to operate on.
  ClockId | is the output clock.

Returns
  - XST_SUCCESS Initialization was successful.
  - XST_FAILURE Initialization was failure.

References XClk_Wiz_Config::BaseAddr, XClk_Wiz::Config, XClk_Wiz::IsReady, and XCLK_WIZ_REG3_USED.

void XClk_Wiz_GetInterruptSettings | ( | XClk_Wiz * | InstancePtr | ) |

XClk_Wiz_GetInterruptSettings will get the information from clock wizard IER and ISR Registers.

Parameters

  InstancePtr | is the XClk_Wiz instance to operate on.

Returns
  None

References XClk_Wiz::ClkIntrEnable, XClk_Wiz::ClkWizIntrStatus, XCLK_WIZ_IER_ALLINTR_MASK, XCLK_WIZ_IER_ALLINTR_SHIFT, XCLK_WIZ_IER_OFFSET, XCLK_WIZ_ISR_ALLINTR_MASK, XCLK_WIZ_ISR_ALLINTR_SHIFT, and XCLK_WIZ_ISR_OFFSET.

s32 XClk_Wiz_GetRate | ( | XClk_Wiz * | InstancePtr,
|  | u32 | ClockId,
|  | u64 * | Rate
| ) |  |

Get the clock frequency for the given ClockId.

Parameters

  InstancePtr | is the XClk_Wiz instance to operate on.
  ClockId | is the output clock.
  Rate | clock rate in Hz.

Returns
  - XST_SUCCESS getting the frequency was successful.
  - XST_FAILURE getting the frequency failed.

References XClk_Wiz::Config, XClk_Wiz_Config::NumClocks, XCLK_WIZ_CLKOUT0_P5FEDGE_MASK, and XCLK_WIZ_REG3_PREDIV2.

Referenced by ClkWiz_Example().

void XClk_Wiz_InterruptClear | ( | XClk_Wiz * | InstancePtr,
|  | u32 | Mask
| ) |  |

XClk_Wiz_InterruptClear will clear the interrupts set in the Interrupt Status Register of the CLK_WIZ core.

Parameters

  InstancePtr | is the XClk_Wiz instance to operate on
  Mask | is Interrupt Mask with bits set for corresponding interrupt to be cleared in the Interrupt Status register

Returns
  None

Note
  None

References XCLK_WIZ_IER_ALLINTR_MASK.

Referenced by XClk_Wiz_IntrHandler().

void XClk_Wiz_InterruptDisable | ( | XClk_Wiz * | InstancePtr,
|  | u32 | Mask
| ) |  |

XClk_Wiz_InterruptDisable will disable the interrupts present in the interrupt mask passed onto the function.

Parameters

  InstancePtr | is the XClk_Wiz instance to operate on
  Mask | is the interrupt mask which need to be enabled in core

Returns
  None

Note
  None

References XCLK_WIZ_IER_ALLINTR_MASK.

void XClk_Wiz_InterruptEnable | ( | XClk_Wiz * | InstancePtr,
|  | u32 | Mask
| ) |  |

XClk_Wiz_InterruptEnable will enable the interrupts present in the interrupt mask passed onto the function.

Parameters

  InstancePtr | is the XClk_Wiz instance to operate on
  Mask | is the interrupt mask which need to be enabled in core

Returns
  None

Note
  None

References XCLK_WIZ_IER_ALLINTR_MASK.

Referenced by ClkWiz_IntrExample().

u32 XClk_Wiz_InterruptGetEnabled | ( | XClk_Wiz * | InstancePtr | ) |

XClk_Wiz_InterruptGetEnabled will get the interrupt mask set (enabled) in the CLK_WIZ core.

Parameters

  InstancePtr | is the XClk_Wiz instance to operate on

Returns
  Interrupt Mask with bits set for corresponding interrupt in Interrupt enable register

Note
  None

u32 XClk_Wiz_InterruptGetStatus | ( | XClk_Wiz * | InstancePtr | ) |

XClk_Wiz_InterruptGetStatus will get the list of interrupts pending in the Interrupt Status Register of the CLK_WIZ core.

Parameters

  InstancePtr | is the XClk_Wiz instance to operate on

Returns
  Interrupt Mask with bits set for corresponding interrupt in Interrupt Status register

Note
  None

Referenced by XClk_Wiz_IntrHandler().

void XClk_Wiz_IntrHandler | ( | void * | InstancePtr | ) |

This function is the interrupt handler for the CLK_WIZ core.

This handler reads the pending interrupt from the Interrupt Status register determines the source of the interrupts and calls the respective callbacks for the interrupts that are enabled in Interrupt Enable register and finally clears the interrupts.

The application is responsible for connecting this function to the interrupt system. Application beyond this core is also responsible for providing callbacks to handle interrupts and installing the callbacks using XClk_Wiz_SetCallBack() during initialization phase.

Parameters

  InstancePtr | is a pointer to the XClk_Wiz core instance.

Returns
  None

Note
  Interrupt should be enabled to execute interrupt handler.

References XClk_Wiz::ClkGlitchCallBack, XClk_Wiz::ClkGlitchRef, XClk_Wiz::ClkOutOfRangeCallBack, XClk_Wiz::ClkOutOfRangeRef, XClk_Wiz::ClkStopCallBack, XClk_Wiz::ClkStopRef, XClk_Wiz::IsReady, XClk_Wiz_InterruptClear(), XClk_Wiz_InterruptGetStatus(), XCLK_WIZ_ISR_CLKALL_GLITCH_MASK, XCLK_WIZ_ISR_CLKALL_MAXFREQ_MASK, XCLK_WIZ_ISR_CLKALL_MINFREQ_MASK, and XCLK_WIZ_ISR_CLKALL_STOP_MASK.

Referenced by ClkWiz_IntrExample(), and SetupInterruptSystem().

XClk_Wiz_Config * XClk_Wiz_LookupConfig | ( | u32 | DeviceId | ) |

Look up the hardware configuration for a device instance.

Parameters

  DeviceId | is the unique device ID of the device to lookup for

Returns
  The reference to the configuration record in the configuration table (in xclk_wiz_g.c) corresponding to the Device ID or if not found, a NULL pointer is returned.

Note
  None

Referenced by ClkWiz_Example(), and ClkWiz_IntrExample().

int XClk_Wiz_SetCallBack | ( | XClk_Wiz * | InstancePtr,
|  | u32 | HandleType,
|  | void * | CallBackFunc,
|  | void * | CallBackRef
| ) |  |

This routine installs an asynchronous callback function for the given HandlerType:

    HandlerType                             Invoked by this driver when:
    -----------------------  --------------------------------------------------
    XCLK_WIZ_HANDLER_CLK_OUTOF_RANGE        Clock under flow/over flow
    XCLK_WIZ_HANDLER_CLK_GLITCH             Clock Glitch
    XCLK_WIZ_HANDLER_CLK_STOP               Clock Stop
    XCLK_WIZ_HANDLER_OTHERERROR             Any other type of interrupts

Parameters

  InstancePtr | is the XClk_Wiz instance to operate on
  HandleType | is the type of call back to be registered.
  CallBackFunc | is the pointer to a call back funtion which is called when a particular event occurs.
  CallBackRef | is a void pointer to data to be referenced to by the CallBackFunc

Returns
  - XST_SUCCESS when handler is installed.

- XST_INVALID_PARAM when HandlerType is invalid.

Note
  Invoking this function for a handler that already has been installed replaces it with the new handler.

References XClk_Wiz::ClkGlitchCallBack, XClk_Wiz::ClkGlitchRef, XClk_Wiz::ClkOutOfRangeCallBack, XClk_Wiz::ClkOutOfRangeRef, XClk_Wiz::ClkStopCallBack, XClk_Wiz::ClkStopRef, XClk_Wiz::ErrorCallBack, XClk_Wiz::ErrRef, and XClk_Wiz::IsReady.

Referenced by ClkWiz_IntrExample(), and SetupInterruptSystem().

void XClk_Wiz_SetInputRate | ( | XClk_Wiz * | InstancePtr,
|  | double | Rate
| ) |  |

Change the Input frequency to the given rate.

Parameters

  InstancePtr | is the XClk_Wiz instance to operate on.
  Rate | is the frequency for which is to be set.

Returns
  None

Note
  Should be called only if the input provider clock is changed eg input clock is si570.

References XClk_Wiz::Config, XClk_Wiz::IsReady, and XClk_Wiz_Config::PrimInClkFreq.

s32 XClk_Wiz_SetLeafRateHz | ( | XClk_Wiz * | InstancePtr,
|  | u32 | ClockId,
|  | u64 | SetRate
| ) |  |

Set the clock rate frequency for the given ClockId.

Parameters

  InstancePtr | is the XClk_Wiz instance to operate on.
  ClockId | is the output clock.
  SetRate | clock rate in Hz.

Returns
  - XST_SUCCESS Setting the rate was successful.
  - XST_FAILURE Setting rate was failed.

References XClk_Wiz::IsReady.

Referenced by ClkWiz_Example().

void XClk_Wiz_SetMinErr | ( | XClk_Wiz * | InstancePtr,
|  | u64 | Minerr
| ) |  |

Set the Minimum error that can be tolerated.

Parameters

  InstancePtr | is the XClk_Wiz instance to operate on.
  Minerr | is the error margin that can be tolerated in Hz.

Returns
  None

Note
  Should be called only if there is only one output clock.

References XClk_Wiz::IsReady.

u32 XClk_Wiz_SetRate | ( | XClk_Wiz * | InstancePtr,
|  | u64 | SetRate
| ) |  |

Change the frequency to the given rate.

Parameters

  InstancePtr | is the XClk_Wiz instance to operate on.
  SetRate | is the frequency for which is requested in MHz.

Returns
  - XST_SUCCESS frequency setting was successful.
  - XST_FAILURE frequency setting failed.

Note
  Should be called only if there is only one output clock.

References XClk_Wiz_Config::BaseAddr, XClk_Wiz::Config, XClk_Wiz::IsReady, and XClk_Wiz_Config::NumClocks.

u32 XClk_Wiz_SetRateHz | ( | XClk_Wiz * | InstancePtr,
|  | u64 | SetRate
| ) |  |

Change the frequency to the given rate in Hz.

Parameters

  InstancePtr | is the XClk_Wiz instance to operate on.
  SetRate | is the frequency in Hz to be set.

Returns
  - XST_SUCCESS Frequency setting was successful.
  - XST_FAILURE frequency setting failed.

Note
  Should be called only if there is only one output clock.

References XClk_Wiz_Config::BaseAddr, XClk_Wiz::Config, XClk_Wiz::IsReady, and XClk_Wiz_Config::NumClocks.

Referenced by ClkWiz_Example().

u32 XClk_Wiz_WaitForLock | ( | XClk_Wiz * | InstancePtr | ) |

Wait till the clocking wizard is locked to the frequency.

Parameters

  InstancePtr | is the XClk_Wiz instance to operate on.

Returns
  - XST_SUCCESS if lock was successful.
  - XST_FAILURE on timeout.

References XClk_Wiz::IsReady, and XCLK_WIZ_STATUS_OFFSET.

Referenced by ClkWiz_Example().