| scugic Vitis Drivers API Documentation

- Overview
- Data Structures
- APIs
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Data Structures | Macros | Functions | Variables
SCUGIC APIs

## Data Structures
struct | XScuGic_Config
| This typedef contains configuration information for the device. More...
struct | XScuGic
| The XScuGic driver instance data. More...

## Macros
#define | DEFAULT_PRIORITY 0xa0a0a0a0U
| Default value for priority_level register. More...
#define | XSCUGIC_H
| < prevent circular inclusions More...
#define | DEFAULT_PRIORITY 0xa0a0a0a0U
| Default value for priority_level register. More...
#define | XSCUGIC_HW_H
| < prevent circular inclusions More...
#define | XSCUGIC_MAX_NUM_INTR_INPUTS 195U
| Maximum number of interrupt defined by Zynq Ultrascale Mp. More...
#define | XSCUGIC_SPI_INT_ID_START 0x20U
| First Interrupt Id for SPI interrupts. More...
#define | XSCUGIC_MAX_INTR_PRIO_VAL 248U
| The maximum priority value that can be used in the GIC. More...
#define | XSCUGIC_INTR_PRIO_MASK 0x000000F8U
| The Interrupt priority mask value. More...
#define | XSCUGIC_PEND_INTID_MASK 0x000003FFU
| Pending Interrupt ID. More...
#define | XSCUGIC_PCELL_ID 0xB105F00DU
| PCELL ID value. More...

## Functions
s32 | XScuGic_DeviceInitialize (u32 DeviceId)
| Initializes the GIC based on the device ID. More...
void | XScuGic_DeviceInterruptHandler (void *DeviceId)
| This function is the primary interrupt handler for the driver. More...
void | XScuGic_RegisterHandler (UINTPTR BaseAddress, s32 InterruptID, Xil_InterruptHandler IntrHandler, void *CallBackRef)
| Register a handler function for a specific interrupt ID. More...
void | XScuGic_SetPriTrigTypeByDistAddr (UINTPTR DistBaseAddress, u32 Int_Id, u8 Priority, u8 Trigger)
| Sets the interrupt priority and trigger type for the specificd IRQ source. More...
void | XScuGic_GetPriTrigTypeByDistAddr (UINTPTR DistBaseAddress, u32 Int_Id, u8 *Priority, u8 *Trigger)
| Gets the interrupt priority and trigger type for the specificd IRQ source. More...
void | XScuGic_InterruptMapFromCpuByDistAddr (UINTPTR DistBaseAddress, u8 Cpu_Id, u32 Int_Id)
| Sets the target CPU for the interrupt of a peripheral. More...
void | XScuGic_InterruptUnmapFromCpuByDistAddr (UINTPTR DistBaseAddress, u8 Cpu_Id, u32 Int_Id)
| Unmaps specific SPI interrupt from the target CPU. More...
void | XScuGic_UnmapAllInterruptsFromCpuByDistAddr (UINTPTR DistBaseAddress, u8 Cpu_Id)
| Unmaps all SPI interrupts from the target CPU. More...
void | XScuGic_EnableIntr (UINTPTR DistBaseAddress, u32 Int_Id)
| Enables the interrupt source provided as the argument Int_Id. More...
void | XScuGic_DisableIntr (UINTPTR DistBaseAddress, u32 Int_Id)
| Disables the interrupt source provided as the argument Int_Id so that the interrupt controller will not cause interrupts for the specified Int_Id. More...

## Variables
Xil_InterruptHandler | XScuGic_VectorTableEntry::Handler
| Interrupt Handler. More...
void * | XScuGic_VectorTableEntry::CallBackRef
| CallBackRef is the callback reference passed in by the upper layer when setting the Interrupt handler for specific interrupt ID, and it will passed back to Interrupt handler when it is invoked. More...
u16 | XScuGic_Config::DeviceId
| Unique ID of device. More...
UINTPTR | XScuGic_Config::CpuBaseAddress
| CPU Interface Register base address. More...
UINTPTR | XScuGic_Config::DistBaseAddress
| Distributor Register base address. More...
XScuGic_VectorTableEntry | XScuGic_Config::HandlerTable [XSCUGIC_MAX_NUM_INTR_INPUTS]
| Vector table of interrupt handlers. More...
XScuGic_Config * | XScuGic::Config
| Configuration table entry. More...
u32 | XScuGic::IsReady
| Device is initialized and ready. More...
u32 | XScuGic::UnhandledInterrupts
| Intc Statistics. More...
XScuGic_Config | XScuGic_ConfigTable [XPAR_XSCUGIC_NUM_INSTANCES]
| This table contains configuration information for each GIC device in the system. More...

## EFUSE status Register information
EFUSE Status Register
#define | EFUSE_STATUS_OFFSET 0x10
#define | EFUSE_STATUS_CPU_MASK 0x80
#define | ARMA9
| ARMA9 macro to identify cortexA9. More...

## GICD_CTLR Register information
GICD_CTLR Status Register
XScuGic_Config | XScuGic_ConfigTable []
| Config table. More...
s32 | XScuGic_CfgInitialize (XScuGic *InstancePtr, XScuGic_Config *ConfigPtr, u32 EffectiveAddr)
| CfgInitialize a specific interrupt controller instance/driver. More...
s32 | XScuGic_Connect (XScuGic *InstancePtr, u32 Int_Id, Xil_InterruptHandler Handler, void *CallBackRef)
| Makes the connection between the Int_Id of the interrupt source and the associated handler that is to run when the interrupt is recognized. More...
void | XScuGic_Disconnect (XScuGic *InstancePtr, u32 Int_Id)
| Updates the interrupt table with the Null Handler and NULL arguments at the location pointed at by the Int_Id. More...
void | XScuGic_Enable (XScuGic *InstancePtr, u32 Int_Id)
| Enables the interrupt source provided as the argument Int_Id. More...
void | XScuGic_Disable (XScuGic *InstancePtr, u32 Int_Id)
| Disables the interrupt source provided as the argument Int_Id such that the interrupt controller will not cause interrupts for the specified Int_Id. More...
s32 | XScuGic_SoftwareIntr (XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Identifier)
| Allows software to simulate an interrupt in the interrupt controller. More...
void | XScuGic_SetPriorityTriggerType (XScuGic *InstancePtr, u32 Int_Id, u8 Priority, u8 Trigger)
| Sets the interrupt priority and trigger type for the specificd IRQ source. More...
void | XScuGic_GetPriorityTriggerType (XScuGic *InstancePtr, u32 Int_Id, u8 *Priority, u8 *Trigger)
| Gets the interrupt priority and trigger type for the specificd IRQ source. More...
void | XScuGic_InterruptMaptoCpu (XScuGic *InstancePtr, u8 Cpu_Identifier, u32 Int_Id)
| Sets the target CPU for the interrupt of a peripheral. More...
void | XScuGic_InterruptUnmapFromCpu (XScuGic *InstancePtr, u8 Cpu_Identifier, u32 Int_Id)
| Unmaps specific SPI interrupt from the target CPU. More...
void | XScuGic_UnmapAllInterruptsFromCpu (XScuGic *InstancePtr, u8 Cpu_Identifier)
| Unmaps all SPI interrupts from the target CPU. More...
void | XScuGic_Stop (XScuGic *InstancePtr)
| Checks if the interrupt target register contains all interrupts to be targeted for current CPU. More...
void | XScuGic_SetCpuID (u32 CpuCoreId)
| Updates the CpuId global variable. More...
u32 | XScuGic_GetCpuID (void)
| Returns the CpuId variable. More...
u8 | XScuGic_IsInitialized (u32 DeviceId)
| Checks whether the XScGic is initialized or not given the device ID. More...
XScuGic_Config * | XScuGic_LookupConfig (u16 DeviceId)
| Looks up the device configuration based on the unique device ID. More...
XScuGic_Config * | XScuGic_LookupConfigBaseAddr (UINTPTR BaseAddress)
| Looks up the device configuration based on the BaseAddress. More...
void | XScuGic_InterruptHandler (XScuGic *InstancePtr)
| This function is the primary interrupt handler for the driver. More...
s32 | XScuGic_SelfTest (XScuGic *InstancePtr)
| Runs a self-test on the driver/device. More...
#define | XSCUGIC500_DCTLR_ARE_NS_ENABLE 0x20
#define | XSCUGIC500_DCTLR_ARE_S_ENABLE 0x10
#define | XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data)
| Writes the given CPU Interface register. More...
#define | XScuGic_CPUReadReg(InstancePtr, RegOffset) (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
| Reads the given CPU Interface register. More...
#define | XScuGic_DistWriteReg(InstancePtr, RegOffset, Data)
| Writes the given Distributor Interface register. More...
#define | XScuGic_DistReadReg(InstancePtr, RegOffset) (XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
| Reads the given Distributor Interface register. More...

## Distributor Interface Register Map
Define the offsets from the base address for all Distributor registers of the interrupt controller, some registers may be reserved in the hardware device.
#define | XSCUGIC_DIST_EN_OFFSET 0x00000000U
| Distributor Enable Register. More...
#define | XSCUGIC_IC_TYPE_OFFSET 0x00000004U
| Interrupt Controller Type Register. More...
#define | XSCUGIC_DIST_IDENT_OFFSET 0x00000008U
| Implementor ID Register. More...
#define | XSCUGIC_SECURITY_OFFSET 0x00000080U
| Interrupt Security Register. More...
#define | XSCUGIC_ENABLE_SET_OFFSET 0x00000100U
| Enable Set Register. More...
#define | XSCUGIC_DISABLE_OFFSET 0x00000180U
| Enable Clear Register. More...
#define | XSCUGIC_PENDING_SET_OFFSET 0x00000200U
| Pending Set Register. More...
#define | XSCUGIC_PENDING_CLR_OFFSET 0x00000280U
| Pending Clear Register. More...
#define | XSCUGIC_ACTIVE_OFFSET 0x00000300U
| Active Status Register. More...
#define | XSCUGIC_PRIORITY_OFFSET 0x00000400U
| Priority Level Register. More...
#define | XSCUGIC_SPI_TARGET_OFFSET 0x00000800U
| SPI Target Register 0x800-0x8FB. More...
#define | XSCUGIC_INT_CFG_OFFSET 0x00000C00U
| Interrupt Configuration Register 0xC00-0xCFC. More...
#define | XSCUGIC_PPI_STAT_OFFSET 0x00000D00U
| PPI Status Register. More...
#define | XSCUGIC_SPI_STAT_OFFSET 0x00000D04U
| SPI Status Register 0xd04-0xd7C. More...
#define | XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U
| AHB Configuration Register. More...
#define | XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U
| Software Triggered Interrupt Register. More...
#define | XSCUGIC_PERPHID_OFFSET 0x00000FD0U
| Peripheral ID Reg. More...
#define | XSCUGIC_PCELLID_OFFSET 0x00000FF0U
| Pcell ID Register. More...

## Distributor Enable Register
Controls if the distributor response to external interrupt inputs.
#define | XSCUGIC_EN_INT_MASK 0x00000001U
| Interrupt In Enable. More...

## Interrupt Controller Type Register
#define | XSCUGIC_LSPI_MASK 0x0000F800U
| Number of Lockable Shared Peripheral Interrupts. More...
#define | XSCUGIC_DOMAIN_MASK 0x00000400U
| Number os Security domains. More...
#define | XSCUGIC_CPU_NUM_MASK 0x000000E0U
| Number of CPU Interfaces. More...
#define | XSCUGIC_NUM_INT_MASK 0x0000001FU
| Number of Interrupt IDs. More...

## Implementor ID Register
Implementor and revision information.
#define | XSCUGIC_REV_MASK 0x00FFF000U
| Revision Number. More...
#define | XSCUGIC_IMPL_MASK 0x00000FFFU
| Implementor. More...

## Interrupt Security Registers
Each bit controls the security level of an interrupt, either secure or non secure. These registers can only be accessed using secure read and write. There are registers for each of the CPU interfaces at offset 0x080. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 32 of these registers staring at location 0x084.
#define | XSCUGIC_INT_NS_MASK 0x00000001U
| Each bit corresponds to an INT_ID. More...

## Enable Set Register
Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a bit to 0. There are registers for each of the CPU interfaces at offset 0x100. With up to 8 registers aliased to the same address. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 32 of these registers staring at location 0x104.
#define | XSCUGIC_INT_EN_MASK 0x00000001U
| Each bit corresponds to an INT_ID. More...

## Enable Clear Register
Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and sets the corresponding bit to 0. There are registers for each of the CPU interfaces at offset 0x180. With up to 8 registers aliased to the same address. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 32 of these registers staring at location 0x184.
#define | XSCUGIC_INT_CLR_MASK 0x00000001U
| Each bit corresponds to an INT_ID. More...

## Pending Set Register
Each bit controls the Pending or Active and Pending state of an interrupt, a 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets an interrupt to the pending state. There are registers for each of the CPU interfaces at offset 0x200. With up to 8 registers aliased to the same address. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 32 of these registers staring at location 0x204.
#define | XSCUGIC_PEND_SET_MASK 0x00000001U
| Each bit corresponds to an INT_ID. More...

## Pending Clear Register
Each bit can clear the Pending or Active and Pending state of an interrupt, a 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 clears the pending state of an interrupt. There are registers for each of the CPU interfaces at offset 0x280. With up to 8 registers aliased to the same address. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 32 of these registers staring at location 0x284.
#define | XSCUGIC_PEND_CLR_MASK 0x00000001U
| Each bit corresponds to an INT_ID. More...

## Active Status Register
Each bit provides the Active status of an interrupt, a 0 is not Active, a 1 is Active. This is a read only register. There are registers for each of the CPU interfaces at offset 0x300. With up to 8 registers aliased to each address. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 32 of these registers staring at location 0x380.
#define | XSCUGIC_ACTIVE_MASK 0x00000001U
| Each bit corresponds to an INT_ID. More...

## Priority Level Register
Each byte in a Priority Level Register sets the priority level of an interrupt. Reading the register provides the priority level of an interrupt. There are registers for each of the CPU interfaces at offset 0x400 through 0x41C. With up to 8 registers aliased to each address. 0 is highest priority, 0xFF is lowest. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 255 of these registers staring at location 0x420.
#define | XSCUGIC_PRIORITY_MASK 0x000000FFU
| Each Byte corresponds to an INT_ID. More...
#define | XSCUGIC_PRIORITY_MAX 0x000000FFU
| Highest value of a priority actually the lowest priority. More...

## SPI Target Register 0x800-0x8FB
Each byte references a separate SPI and programs which of the up to 8 CPU interfaces are sent a Pending interrupt. There are registers for each of the CPU interfaces at offset 0x800 through 0x81C. With up to 8 registers aliased to each address. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 255 of these registers staring at location 0x820. This driver does not support multiple CPU interfaces. These are included for complete documentation.
#define | XSCUGIC_SPI_CPU7_MASK 0x00000080U
| CPU 7 Mask. More...
#define | XSCUGIC_SPI_CPU6_MASK 0x00000040U
| CPU 6 Mask. More...
#define | XSCUGIC_SPI_CPU5_MASK 0x00000020U
| CPU 5 Mask. More...
#define | XSCUGIC_SPI_CPU4_MASK 0x00000010U
| CPU 4 Mask. More...
#define | XSCUGIC_SPI_CPU3_MASK 0x00000008U
| CPU 3 Mask. More...
#define | XSCUGIC_SPI_CPU2_MASK 0x00000004U
| CPU 2 Mask. More...
#define | XSCUGIC_SPI_CPU1_MASK 0x00000002U
| CPU 1 Mask. More...
#define | XSCUGIC_SPI_CPU0_MASK 0x00000001U
| CPU 0 Mask. More...

## Interrupt Configuration Register 0xC00-0xCFC
The interrupt configuration registers program an SFI to be active HIGH level sensitive or rising edge sensitive. Each bit pair describes the configuration for an INT_ID. SFI Read Only b10 always PPI Read Only depending on how the PPIs are configured. b01 Active HIGH level sensitive b11 Rising edge sensitive SPI LSB is read only. b01 Active HIGH level sensitive b11 Rising edge sensitive/ There are registers for each of the CPU interfaces at offset 0xC00 through 0xC04. With up to 8 registers aliased to each address. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 255 of these registers staring at location 0xC08.
#define | XSCUGIC_INT_CFG_MASK 0x00000003U
| Interrupt configuration Mask. More...

## PPI Status Register
Enables an external AMBA master to access the status of the PPI inputs. A CPU can only read the status of its local PPI signals and cannot read the status for other CPUs. This register is aliased for each CPU interface.
#define | XSCUGIC_PPI_C15_MASK 0x00008000U
| PPI Status. More...
#define | XSCUGIC_PPI_C14_MASK 0x00004000U
| PPI Status. More...
#define | XSCUGIC_PPI_C13_MASK 0x00002000U
| PPI Status. More...
#define | XSCUGIC_PPI_C12_MASK 0x00001000U
| PPI Status. More...
#define | XSCUGIC_PPI_C11_MASK 0x00000800U
| PPI Status. More...
#define | XSCUGIC_PPI_C10_MASK 0x00000400U
| PPI Status. More...
#define | XSCUGIC_PPI_C09_MASK 0x00000200U
| PPI Status. More...
#define | XSCUGIC_PPI_C08_MASK 0x00000100U
| PPI Status. More...
#define | XSCUGIC_PPI_C07_MASK 0x00000080U
| PPI Status. More...
#define | XSCUGIC_PPI_C06_MASK 0x00000040U
| PPI Status. More...
#define | XSCUGIC_PPI_C05_MASK 0x00000020U
| PPI Status. More...
#define | XSCUGIC_PPI_C04_MASK 0x00000010U
| PPI Status. More...
#define | XSCUGIC_PPI_C03_MASK 0x00000008U
| PPI Status. More...
#define | XSCUGIC_PPI_C02_MASK 0x00000004U
| PPI Status. More...
#define | XSCUGIC_PPI_C01_MASK 0x00000002U
| PPI Status. More...
#define | XSCUGIC_PPI_C00_MASK 0x00000001U
| PPI Status. More...

## SPI Status Register 0xd04-0xd7C
Enables an external AMBA master to access the status of the SPI inputs. There are up to 63 registers if the maximum number of SPI inputs are configured.
#define | XSCUGIC_SPI_N_MASK 0x00000001U
| Each bit corresponds to an SPI input. More...

## AHB Configuration Register
Provides the status of the CFGBIGEND input signal and allows the endianness of the GIC to be set.
#define | XSCUGIC_AHB_END_MASK 0x00000004U
| 0-GIC uses little Endian, 1-GIC uses Big Endian More...
#define | XSCUGIC_AHB_ENDOVR_MASK 0x00000002U
| 0-Uses CFGBIGEND control, 1-use the AHB_END bit More...
#define | XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U
| State of CFGBIGEND. More...

## Software Triggered Interrupt Register
Controls issuing of software interrupts.
#define | XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U
#define | XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U
| Target List filter b00-Use the target List b01-All CPUs except requester b10-To Requester b11-reserved. More...
#define | XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U
| CPU Target list. More...
#define | XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U
| 0= Use a secure interrupt More...
#define | XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU
| Set to the INTID signaled to the CPU. More...

## CPU Interface Register Map
Define the offsets from the base address for all CPU registers of the interrupt controller, some registers may be reserved in the hardware device.
#define | XSCUGIC_CONTROL_OFFSET 0x00000000U
| CPU Interface Control Register. More...
#define | XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U
| Priority Mask Reg. More...
#define | XSCUGIC_BIN_PT_OFFSET 0x00000008U
| Binary Point Register. More...
#define | XSCUGIC_INT_ACK_OFFSET 0x0000000CU
| Interrupt ACK Reg. More...
#define | XSCUGIC_EOI_OFFSET 0x00000010U
| End of Interrupt Reg. More...
#define | XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U
| Running Priority Reg. More...
#define | XSCUGIC_HI_PEND_OFFSET 0x00000018U
| Highest Pending Interrupt Register. More...
#define | XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU
| Aliased non-Secure Binary Point Register. More...

## Control Register
CPU Interface Control register definitions All bits are defined here although some are not available in the non-secure mode.
#define | XSCUGIC_CNTR_SBPR_MASK 0x00000010U
| Secure Binary Pointer, 0=separate registers, 1=both use bin_pt_s. More...
#define | XSCUGIC_CNTR_FIQEN_MASK 0x00000008U
| Use nFIQ_C for secure interrupts, 0= use IRQ for both, 1=Use FIQ for secure, IRQ for non. More...
#define | XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U
| Ack control for secure or non secure. More...
#define | XSCUGIC_CNTR_EN_NS_MASK 0x00000002U
| Non Secure enable. More...
#define | XSCUGIC_CNTR_EN_S_MASK 0x00000001U
| Secure enable, 0=Disabled, 1=Enabled. More...

## Binary Point Register
Binary Point register definitions
#define | XSCUGIC_BIN_PT_MASK 0x00000007U
| Binary point mask value Value Secure Non-secure b000 0xFE 0xFF b001 0xFC 0xFE b010 0xF8 0xFC b011 0xF0 0xF8 b100 0xE0 0xF0 b101 0xC0 0xE0 b110 0x80 0xC0 b111 0x00 0x80. More...

## Interrupt Acknowledge Register
Interrupt Acknowledge register definitions Identifies the current Pending interrupt, and the CPU ID for software interrupts.
#define | XSCUGIC_ACK_INTID_MASK 0x000003FFU
| Interrupt ID. More...
#define | XSCUGIC_CPUID_MASK 0x00000C00U
| CPU ID. More...

## End of Interrupt Register
End of Interrupt register definitions Allows the CPU to signal the GIC when it completes an interrupt service routine.
#define | XSCUGIC_EOI_INTID_MASK 0x000003FFU
| Interrupt ID. More...

## Running Priority Register
Running Priority register definitions Identifies the interrupt priority level of the highest priority active interrupt.
#define | XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU
| Interrupt Priority. More...

## Macro Definition Documentation

#define ARMA9

ARMA9 macro to identify cortexA9.

#define DEFAULT_PRIORITY 0xa0a0a0a0U

Default value for priority_level register.

#define DEFAULT_PRIORITY 0xa0a0a0a0U

Default value for priority_level register.

#define XSCUGIC_ACK_INTID_MASK 0x000003FFU

Interrupt ID.

Referenced by LowInterruptHandler(), XScuGic_DeviceInterruptHandler(), and XScuGic_InterruptHandler().

#define XSCUGIC_ACTIVE_MASK 0x00000001U

Each bit corresponds to an INT_ID.

#define XSCUGIC_ACTIVE_OFFSET 0x00000300U

Active Status Register.

#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U

AHB Configuration Register.

#define XSCUGIC_AHB_END_MASK 0x00000004U

0-GIC uses little Endian, 1-GIC uses Big Endian

#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U

0-Uses CFGBIGEND control, 1-use the AHB_END bit

#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U

State of CFGBIGEND.

#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU

Aliased non-Secure Binary Point Register.

0x00000020 to 0x00000FBC are reserved and should not be read or written to.

#define XSCUGIC_BIN_PT_MASK 0x00000007U

Binary point mask value Value Secure Non-secure b000 0xFE 0xFF b001 0xFC 0xFE b010 0xF8 0xFC b011 0xF0 0xF8 b100 0xE0 0xF0 b101 0xC0 0xE0 b110 0x80 0xC0 b111 0x00 0x80.

#define XSCUGIC_BIN_PT_OFFSET 0x00000008U

Binary Point Register.

#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U

Ack control for secure or non secure.

#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U

Non Secure enable.

#define XSCUGIC_CNTR_EN_S_MASK 0x00000001U

Secure enable, 0=Disabled, 1=Enabled.

#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U

Use nFIQ_C for secure interrupts, 0= use IRQ for both, 1=Use FIQ for secure, IRQ for non.

#define XSCUGIC_CNTR_SBPR_MASK 0x00000010U

Secure Binary Pointer, 0=separate registers, 1=both use bin_pt_s.

#define XSCUGIC_CONTROL_OFFSET 0x00000000U

CPU Interface Control Register.

#define XSCUGIC_CPU_NUM_MASK 0x000000E0U

Number of CPU Interfaces.

#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U

Priority Mask Reg.

#define XSCUGIC_CPUID_MASK 0x00000C00U

CPU ID.

#define XScuGic_CPUReadReg | ( |  | InstancePtr,
|  |  | RegOffset
| ) |  | (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))

Reads the given CPU Interface register.

Parameters

  InstancePtr | Pointer to the instance to be worked on.
  RegOffset | Rregister offset to be read.

Returns
  32-bit value of the register

Note
  C-style signature: u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)

Referenced by XScuGic_InterruptHandler().

#define XScuGic_CPUWriteReg | ( |  | InstancePtr,
|  |  | RegOffset,
|  |  | Data
| ) |  |

Value:
(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
((u32)(Data))))
XScuGic_WriteReg
#define XScuGic_WriteReg(BaseAddress, RegOffset, Data)
Writes the given Intc register.
Definition: xscugic_hw.h:786

Writes the given CPU Interface register.

Parameters

  InstancePtr | Pointer to the instance to be worked on.
  RegOffset | Register offset to be written.
  Data | 32-bit value to write to the register.

Returns
  None.

Note
  C-style signature: void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)

Referenced by XScuGic_InterruptHandler().

#define XSCUGIC_DISABLE_OFFSET 0x00000180U

Enable Clear Register.

Referenced by XScuGic_Disable(), XScuGic_DisableIntr(), XScuGic_Disconnect(), and XScuGic_Stop().

#define XSCUGIC_DIST_EN_OFFSET 0x00000000U

Distributor Enable Register.

Referenced by XScuGic_IsInitialized(), and XScuGic_Stop().

#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U

Implementor ID Register.

#define XScuGic_DistReadReg | ( |  | InstancePtr,
|  |  | RegOffset
| ) |  | (XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))

Reads the given Distributor Interface register.

Parameters

  InstancePtr | Pointer to the instance to be worked on.
  RegOffset | Register offset to be read.

Returns
  The 32-bit value of the register.

Note
  C-style signature: u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)

Referenced by XScuGic_GetPriorityTriggerType(), XScuGic_InterruptMaptoCpu(), XScuGic_InterruptUnmapFromCpu(), XScuGic_SelfTest(), XScuGic_SetPriorityTriggerType(), XScuGic_Stop(), and XScuGic_UnmapAllInterruptsFromCpu().

#define XScuGic_DistWriteReg | ( |  | InstancePtr,
|  |  | RegOffset,
|  |  | Data
| ) |  |

Value:
(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
((u32)(Data))))
XScuGic_WriteReg
#define XScuGic_WriteReg(BaseAddress, RegOffset, Data)
Writes the given Intc register.
Definition: xscugic_hw.h:786

Writes the given Distributor Interface register.

Parameters

  InstancePtr | Pointer to the instance to be worked on.
  RegOffset | Register offset to be written.
  Data | 32-bit value to write to the register.

Returns
  None.

Note
  C-style signature: void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)

Referenced by XScuGic_Disable(), XScuGic_Disconnect(), XScuGic_Enable(), XScuGic_InterruptMaptoCpu(), XScuGic_InterruptUnmapFromCpu(), XScuGic_SetPriorityTriggerType(), XScuGic_SoftwareIntr(), XScuGic_Stop(), and XScuGic_UnmapAllInterruptsFromCpu().

#define XSCUGIC_DOMAIN_MASK 0x00000400U

Number os Security domains.

#define XSCUGIC_EN_INT_MASK 0x00000001U

Interrupt In Enable.

Referenced by XScuGic_IsInitialized(), and XScuGic_Stop().

#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U

Enable Set Register.

Referenced by XScuGic_Enable(), and XScuGic_EnableIntr().

#define XSCUGIC_EOI_INTID_MASK 0x000003FFU

Interrupt ID.

#define XSCUGIC_EOI_OFFSET 0x00000010U

End of Interrupt Reg.

Referenced by LowInterruptHandler(), XScuGic_DeviceInterruptHandler(), and XScuGic_InterruptHandler().

#define XSCUGIC_H

< prevent circular inclusions

by using protection macros

#define XSCUGIC_HI_PEND_OFFSET 0x00000018U

Highest Pending Interrupt Register.

#define XSCUGIC_HW_H

< prevent circular inclusions

by using protection macros

#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U

Interrupt Controller Type Register.

#define XSCUGIC_IMPL_MASK 0x00000FFFU

Implementor.

#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU

Interrupt ACK Reg.

Referenced by LowInterruptHandler(), XScuGic_DeviceInterruptHandler(), and XScuGic_InterruptHandler().

#define XSCUGIC_INT_CFG_MASK 0x00000003U

Interrupt configuration Mask.

Referenced by XScuGic_GetPriorityTriggerType(), XScuGic_GetPriTrigTypeByDistAddr(), XScuGic_SetPriorityTriggerType(), and XScuGic_SetPriTrigTypeByDistAddr().

#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U

Interrupt Configuration Register 0xC00-0xCFC.

#define XSCUGIC_INT_CLR_MASK 0x00000001U

Each bit corresponds to an INT_ID.

#define XSCUGIC_INT_EN_MASK 0x00000001U

Each bit corresponds to an INT_ID.

#define XSCUGIC_INT_NS_MASK 0x00000001U

Each bit corresponds to an INT_ID.

#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U

The Interrupt priority mask value.

Referenced by XScuGic_SetPriorityTriggerType(), and XScuGic_SetPriTrigTypeByDistAddr().

#define XSCUGIC_LSPI_MASK 0x0000F800U

Number of Lockable Shared Peripheral Interrupts.

#define XSCUGIC_MAX_INTR_PRIO_VAL 248U

The maximum priority value that can be used in the GIC.

Referenced by XScuGic_SetPriorityTriggerType(), and XScuGic_SetPriTrigTypeByDistAddr().

#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U

Maximum number of interrupt defined by Zynq Ultrascale Mp.

Referenced by LowInterruptHandler(), XScuGic_CfgInitialize(), XScuGic_InterruptHandler(), XScuGic_Stop(), XScuGic_UnmapAllInterruptsFromCpu(), and XScuGic_UnmapAllInterruptsFromCpuByDistAddr().

#define XSCUGIC_NUM_INT_MASK 0x0000001FU

Number of Interrupt IDs.

#define XSCUGIC_PCELL_ID 0xB105F00DU

PCELL ID value.

Referenced by XScuGic_SelfTest().

#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U

Pcell ID Register.

Referenced by XScuGic_SelfTest().

#define XSCUGIC_PEND_CLR_MASK 0x00000001U

Each bit corresponds to an INT_ID.

#define XSCUGIC_PEND_INTID_MASK 0x000003FFU

Pending Interrupt ID.

#define XSCUGIC_PEND_SET_MASK 0x00000001U

Each bit corresponds to an INT_ID.

#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U

Pending Clear Register.

#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U

Pending Set Register.

#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U

Peripheral ID Reg.

#define XSCUGIC_PPI_C00_MASK 0x00000001U

PPI Status.

#define XSCUGIC_PPI_C01_MASK 0x00000002U

PPI Status.

#define XSCUGIC_PPI_C02_MASK 0x00000004U

PPI Status.

#define XSCUGIC_PPI_C03_MASK 0x00000008U

PPI Status.

#define XSCUGIC_PPI_C04_MASK 0x00000010U

PPI Status.

#define XSCUGIC_PPI_C05_MASK 0x00000020U

PPI Status.

#define XSCUGIC_PPI_C06_MASK 0x00000040U

PPI Status.

#define XSCUGIC_PPI_C07_MASK 0x00000080U

PPI Status.

#define XSCUGIC_PPI_C08_MASK 0x00000100U

PPI Status.

#define XSCUGIC_PPI_C09_MASK 0x00000200U

PPI Status.

#define XSCUGIC_PPI_C10_MASK 0x00000400U

PPI Status.

#define XSCUGIC_PPI_C11_MASK 0x00000800U

PPI Status.

#define XSCUGIC_PPI_C12_MASK 0x00001000U

PPI Status.

#define XSCUGIC_PPI_C13_MASK 0x00002000U

PPI Status.

#define XSCUGIC_PPI_C14_MASK 0x00004000U

PPI Status.

#define XSCUGIC_PPI_C15_MASK 0x00008000U

PPI Status.

#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U

PPI Status Register.

#define XSCUGIC_PRIORITY_MASK 0x000000FFU

Each Byte corresponds to an INT_ID.

Referenced by XScuGic_GetPriorityTriggerType(), XScuGic_GetPriTrigTypeByDistAddr(), XScuGic_SetPriorityTriggerType(), and XScuGic_SetPriTrigTypeByDistAddr().

#define XSCUGIC_PRIORITY_MAX 0x000000FFU

Highest value of a priority actually the lowest priority.

#define XSCUGIC_PRIORITY_OFFSET 0x00000400U

Priority Level Register.

#define XSCUGIC_REV_MASK 0x00FFF000U

Revision Number.

#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U

Running Priority Reg.

#define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU

Interrupt Priority.

#define XSCUGIC_SECURITY_OFFSET 0x00000080U

Interrupt Security Register.

#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U

CPU Target list.

Referenced by XScuGic_SoftwareIntr().

#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU

Set to the INTID signaled to the CPU.

Referenced by XScuGic_SoftwareIntr().

#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U

Software Triggered Interrupt Register.

Referenced by XScuGic_SoftwareIntr().

#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U

0= Use a secure interrupt

#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U

Target List filter b00-Use the target List b01-All CPUs except requester b10-To Requester b11-reserved.

#define XSCUGIC_SPI_CPU0_MASK 0x00000001U

CPU 0 Mask.

Referenced by ScuGicExample().

#define XSCUGIC_SPI_CPU1_MASK 0x00000002U

CPU 1 Mask.

#define XSCUGIC_SPI_CPU2_MASK 0x00000004U

CPU 2 Mask.

#define XSCUGIC_SPI_CPU3_MASK 0x00000008U

CPU 3 Mask.

#define XSCUGIC_SPI_CPU4_MASK 0x00000010U

CPU 4 Mask.

#define XSCUGIC_SPI_CPU5_MASK 0x00000020U

CPU 5 Mask.

#define XSCUGIC_SPI_CPU6_MASK 0x00000040U

CPU 6 Mask.

#define XSCUGIC_SPI_CPU7_MASK 0x00000080U

CPU 7 Mask.

#define XSCUGIC_SPI_INT_ID_START 0x20U

First Interrupt Id for SPI interrupts.

Referenced by XScuGic_Disable(), XScuGic_DisableIntr(), XScuGic_Enable(), XScuGic_EnableIntr(), XScuGic_GetPriorityTriggerType(), XScuGic_GetPriTrigTypeByDistAddr(), XScuGic_InterruptMapFromCpuByDistAddr(), XScuGic_InterruptMaptoCpu(), XScuGic_InterruptUnmapFromCpu(), XScuGic_InterruptUnmapFromCpuByDistAddr(), XScuGic_SetPriorityTriggerType(), and XScuGic_SetPriTrigTypeByDistAddr().

#define XSCUGIC_SPI_N_MASK 0x00000001U

Each bit corresponds to an SPI input.

#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U

SPI Status Register 0xd04-0xd7C.

#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U

SPI Target Register 0x800-0x8FB.

## Function Documentation

s32 XScuGic_CfgInitialize | ( | XScuGic * | InstancePtr,
|  | XScuGic_Config * | ConfigPtr,
|  | u32 | EffectiveAddr
| ) |  |

CfgInitialize a specific interrupt controller instance/driver.

The initialization entails:

- Initialize fields of the XScuGic structure
- Initial vector table with stub function calls
- All interrupt sources are disabled

Parameters

  InstancePtr | Pointer to the XScuGic instance.
  ConfigPtr | Pointer to a config table for the particular device this driver is associated with.
  EffectiveAddr | Device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use Config->BaseAddress for this parameters, passing the physical address instead.

Returns
  - XST_SUCCESS if initialization was successful

References XScuGic::Config, XScuGic_Config::DistBaseAddress, XScuGic_Config::HandlerTable, XScuGic::IsReady, XSCUGIC_MAX_NUM_INTR_INPUTS, and XScuGic_Stop().

Referenced by ScuGicExample(), ScuGicInterruptSetup(), and ScuGicSelfTestExample().

s32 XScuGic_Connect | ( | XScuGic * | InstancePtr,
|  | u32 | Int_Id,
|  | Xil_InterruptHandler | Handler,
|  | void * | CallBackRef
| ) |  |

Makes the connection between the Int_Id of the interrupt source and the associated handler that is to run when the interrupt is recognized.

The argument provided in this call as the Callbackref is used as the argument for the handler when it is called.

Parameters

  InstancePtr | Pointer to the XScuGic instance.
  Int_Id | contains the ID of the interrupt source and should be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
  Handler | Handler for interrupt.
  CallBackRef | Instance pointer of the connecting driver.

Returns

          - XST_SUCCESS if the handler was connected correctly.

WARNING: The handler provided as an argument will overwrite any handler that was previously connected.

References XScuGic::Config, XScuGic_Config::HandlerTable, and XScuGic::IsReady.

Referenced by ScuGicExample().

s32 XScuGic_DeviceInitialize | ( | u32 | DeviceId | ) |

Initializes the GIC based on the device ID.

The initialization entails:

- Initialize distributor interface
- Initialize cpu interface

Parameters

  DeviceId | Device id to be worked on.

Returns

- XST_SUCCESS if initialization was successful

References XScuGic_ConfigTable.

void XScuGic_DeviceInterruptHandler | ( | void * | DeviceId | ) |

This function is the primary interrupt handler for the driver.

It must be connected to the interrupt source such that it is called when an interrupt of the interrupt controller is active. It will resolve which interrupts are active and enabled and call the appropriate interrupt handler. It uses the Interrupt Type information to determine when to acknowledge the interrupt. Highest priority interrupts are serviced first.

This function assumes that an interrupt vector table has been previously initialized. It does not verify that entries in the table are valid before calling an interrupt handler.

Parameters

  DeviceId | Unique identifier for the ScuGic device.

Returns
  None.

References XSCUGIC_ACK_INTID_MASK, XScuGic_ConfigTable, XSCUGIC_EOI_OFFSET, XSCUGIC_INT_ACK_OFFSET, XScuGic_ReadReg, and XScuGic_WriteReg.

void XScuGic_Disable | ( | XScuGic * | InstancePtr,
|  | u32 | Int_Id
| ) |  |

Disables the interrupt source provided as the argument Int_Id such that the interrupt controller will not cause interrupts for the specified Int_Id.

The interrupt controller will continue to hold an interrupt condition for the Int_Id, but will not cause an interrupt. This API also unmaps the interrupt for the requesting CPU.

Parameters

  InstancePtr | Pointer to the XScuGic instance.
  Int_Id | Contains the ID of the interrupt source and should be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1

Returns
  None.

References XScuGic::IsReady, XSCUGIC_DISABLE_OFFSET, XScuGic_DistWriteReg, XScuGic_InterruptUnmapFromCpu(), and XSCUGIC_SPI_INT_ID_START.

void XScuGic_DisableIntr | ( | UINTPTR | DistBaseAddress,
|  | u32 | Int_Id
| ) |  |

Disables the interrupt source provided as the argument Int_Id so that the interrupt controller will not cause interrupts for the specified Int_Id.

The interrupt controller will continue to hold an interrupt condition for the Int_Id, but will not cause an interrupt.

Parameters

  Int_Id | Contains the ID of the interrupt source and should be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1.

Returns
  None.

References XSCUGIC_DISABLE_OFFSET, XScuGic_GetCpuID(), XScuGic_InterruptUnmapFromCpuByDistAddr(), XScuGic_ReadReg, XSCUGIC_SPI_INT_ID_START, and XScuGic_WriteReg.

void XScuGic_Disconnect | ( | XScuGic * | InstancePtr,
|  | u32 | Int_Id
| ) |  |

Updates the interrupt table with the Null Handler and NULL arguments at the location pointed at by the Int_Id.

This effectively disconnects that interrupt source from any handler. The interrupt is disabled also.

Parameters

  InstancePtr | Pointer to the XScuGic instance to be worked on.
  Int_Id | Contains the ID of the interrupt source and should be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1

Returns
  None.

References XScuGic::Config, XScuGic_Config::HandlerTable, XScuGic::IsReady, XSCUGIC_DISABLE_OFFSET, and XScuGic_DistWriteReg.

void XScuGic_Enable | ( | XScuGic * | InstancePtr,
|  | u32 | Int_Id
| ) |  |

Enables the interrupt source provided as the argument Int_Id.

Any pending interrupt condition for the specified Int_Id will occur after this function is called. This API also maps the interrupt to the requesting CPU.

Parameters

  InstancePtr | Pointer to the XScuGic instance.
  Int_Id | Contains the ID of the interrupt source and should be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1

Returns
  None.

References XScuGic::IsReady, XScuGic_DistWriteReg, XSCUGIC_ENABLE_SET_OFFSET, XScuGic_InterruptMaptoCpu(), and XSCUGIC_SPI_INT_ID_START.

Referenced by ScuGicExample().

void XScuGic_EnableIntr | ( | UINTPTR | DistBaseAddress,
|  | u32 | Int_Id
| ) |  |

Enables the interrupt source provided as the argument Int_Id.

Any pending interrupt condition for the specified Int_Id will occur after this function is called.

Parameters

  Int_Id | Contains the ID of the interrupt source and should be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1.

Returns
  None.

References XSCUGIC_ENABLE_SET_OFFSET, XScuGic_GetCpuID(), XScuGic_InterruptMapFromCpuByDistAddr(), XScuGic_ReadReg, XSCUGIC_SPI_INT_ID_START, and XScuGic_WriteReg.

u32 XScuGic_GetCpuID | ( | void |  | ) |

Returns the CpuId variable.

Returns
  The CPU core number.

Referenced by XScuGic_DisableIntr(), and XScuGic_EnableIntr().

void XScuGic_GetPriorityTriggerType | ( | XScuGic * | InstancePtr,
|  | u32 | Int_Id,
|  | u8 * | Priority,
|  | u8 * | Trigger
| ) |  |

Gets the interrupt priority and trigger type for the specificd IRQ source.

Parameters

  InstancePtr | Pointer to the instance to be worked on.
  Int_Id | IRQ source number to modify.
  Priority | Pointer to the value of the priority of the IRQ source. This is a return value.
  Trigger | Pointer to the value of the trigger of the IRQ source.

Returns
  Pointer to the value of the trigger of the IRQ source.

References XScuGic::IsReady, XScuGic_DistReadReg, XSCUGIC_INT_CFG_MASK, XSCUGIC_INT_CFG_OFFSET_CALC, XSCUGIC_PRIORITY_MASK, XSCUGIC_PRIORITY_OFFSET_CALC, XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC, XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC, and XSCUGIC_SPI_INT_ID_START.

void XScuGic_GetPriTrigTypeByDistAddr | ( | UINTPTR | DistBaseAddress,
|  | u32 | Int_Id,
|  | u8 * | Priority,
|  | u8 * | Trigger
| ) |  |

Gets the interrupt priority and trigger type for the specificd IRQ source.

Parameters

  DistBaseAddress | Distributor base address
  Int_Id | IRQ source number to modify
  Priority | Pointer to the value of the priority of the IRQ source. This is a return value.
  Trigger | Pointer to the value of the trigger of the IRQ source. This is a return value.

Returns
  None.

Note
  This API has the similar functionality of XScuGic_GetPriority TriggerType() and should be used when there is no InstancePtr.

References XSCUGIC_INT_CFG_MASK, XSCUGIC_INT_CFG_OFFSET_CALC, XSCUGIC_PRIORITY_MASK, XSCUGIC_PRIORITY_OFFSET_CALC, XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC, XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC, XScuGic_ReadReg, and XSCUGIC_SPI_INT_ID_START.

void XScuGic_InterruptHandler | ( | XScuGic * | InstancePtr | ) |

This function is the primary interrupt handler for the driver.

It must be connected to the interrupt source such that it is called when an interrupt of the interrupt controller is active. It will resolve which interrupts are active and enabled and call the appropriate interrupt handler. It uses the Interrupt Type information to determine when to acknowledge the interrupt. Highest priority interrupts are serviced first.

This function assumes that an interrupt vector table has been previously initialized. It does not verify that entries in the table are valid before calling an interrupt handler.

Parameters

  InstancePtr | Pointer to the XScuGic instance.

Returns
  None.

References XScuGic::Config, XScuGic_Config::HandlerTable, XSCUGIC_ACK_INTID_MASK, XScuGic_CPUReadReg, XScuGic_CPUWriteReg, XSCUGIC_EOI_OFFSET, XSCUGIC_INT_ACK_OFFSET, and XSCUGIC_MAX_NUM_INTR_INPUTS.

Referenced by ScuGicInterruptSetup(), and SetUpInterruptSystem().

void XScuGic_InterruptMapFromCpuByDistAddr | ( | UINTPTR | DistBaseAddress,
|  | u8 | Cpu_Id,
|  | u32 | Int_Id
| ) |  |

Sets the target CPU for the interrupt of a peripheral.

Parameters

  DistBaseAddress | Device base address
  Cpu_Id | CPU number from which the interrupt has to be unmapped
  Int_Id | IRQ source number to modify

Returns
  None.

References XSCUGIC_IROUTER_OFFSET_CALC, XScuGic_ReadReg, XSCUGIC_SPI_INT_ID_START, XSCUGIC_SPI_TARGET_OFFSET_CALC, and XScuGic_WriteReg.

Referenced by XScuGic_EnableIntr().

void XScuGic_InterruptMaptoCpu | ( | XScuGic * | InstancePtr,
|  | u8 | Cpu_Identifier,
|  | u32 | Int_Id
| ) |  |

Sets the target CPU for the interrupt of a peripheral.

Parameters

  InstancePtr | Pointer to the instance to be worked on.
  Cpu_Identifier | CPU number for which the interrupt has to be targeted For VERSAL_NET APU: 0 t0 3 bits sepcifies core id and 4 to 7 bits specifies cluster id of the targeted core.
  Int_Id | IRQ source number to modify.

Returns
  None.

References XScuGic_DistReadReg, XScuGic_DistWriteReg, XSCUGIC_IROUTER_OFFSET_CALC, XSCUGIC_SPI_INT_ID_START, and XSCUGIC_SPI_TARGET_OFFSET_CALC.

Referenced by XScuGic_Enable().

void XScuGic_InterruptUnmapFromCpu | ( | XScuGic * | InstancePtr,
|  | u8 | Cpu_Identifier,
|  | u32 | Int_Id
| ) |  |

Unmaps specific SPI interrupt from the target CPU.

Parameters

  InstancePtr | Pointer to the instance to be worked on.
  Cpu_Identifier | CPU number from which the interrupt has to be unmapped. For VERSAL_NET APU: 0 t0 3 bits sepcifies core id and 4 to 7 bits specifies cluster id of the targeted core.
  Int_Id | IRQ source number to modify

Returns
  None.

References XScuGic_DistReadReg, XScuGic_DistWriteReg, XSCUGIC_SPI_INT_ID_START, and XSCUGIC_SPI_TARGET_OFFSET_CALC.

Referenced by XScuGic_Disable().

void XScuGic_InterruptUnmapFromCpuByDistAddr | ( | UINTPTR | DistBaseAddress,
|  | u8 | Cpu_Id,
|  | u32 | Int_Id
| ) |  |

Unmaps specific SPI interrupt from the target CPU.

Parameters

  DistBaseAddress | Device base address
  Cpu_Id | CPU number from which the interrupt has to be unmapped
  Int_Id | IRQ source number to modify

Returns
  None

References XScuGic_ReadReg, XSCUGIC_SPI_INT_ID_START, XSCUGIC_SPI_TARGET_OFFSET_CALC, and XScuGic_WriteReg.

Referenced by XScuGic_DisableIntr().

u8 XScuGic_IsInitialized | ( | u32 | DeviceId | ) |

Checks whether the XScGic is initialized or not given the device ID.

Parameters

  DeviceId | ID of the XScuGic device.

Returns
  Returns 1 if initialized otherwise 0.

References XScuGic_Config::DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, XSCUGIC_EN_INT_MASK, XScuGic_LookupConfig(), and XScuGic_ReadReg.

XScuGic_Config * XScuGic_LookupConfig | ( | u16 | DeviceId | ) |

Looks up the device configuration based on the unique device ID.

A table contains the configuration info for each device in the system.

Parameters

  DeviceId | Unique identifier for a device.

Returns
  A pointer to the XScuGic configuration structure for the specified device, or NULL if the device is not found.

References XScuGic_ConfigTable.

Referenced by ScuGicExample(), ScuGicInterruptSetup(), ScuGicSelfTestExample(), and XScuGic_IsInitialized().

XScuGic_Config * XScuGic_LookupConfigBaseAddr | ( | UINTPTR | BaseAddress | ) |

Looks up the device configuration based on the BaseAddress.

The return value will refer to an entry in the device configuration table defined in the xscugic_g.c file.

Parameters

  BaseAddress | Base address of the device.

Returns
  A pointer to the XScuGic configuration structure for the specified device, or NULL if the device is not found.

References XScuGic_ConfigTable.

void XScuGic_RegisterHandler | ( | UINTPTR | BaseAddress,
|  | s32 | InterruptID,
|  | Xil_InterruptHandler | IntrHandler,
|  | void * | CallBackRef
| ) |  |

Register a handler function for a specific interrupt ID.

The vector table of the interrupt controller is updated, overwriting any previous handler. The handler function will be called when an interrupt occurs for the given interrupt ID.

Parameters

  BaseAddress | CPU Interface Register base address of the interrupt controller whose vector table will be modified.
  InterruptID | Interrupt ID to be associated with the input handler.
  IntrHandler | Function pointer that will be added to the vector table for the given interrupt ID.
  CallBackRef | Argument that will be passed to the new handler function when it is called. This is user-specific.

Returns
  None.

Note
  This function has no effect if the input base address is invalid.

References XScuGic_Config::HandlerTable.

s32 XScuGic_SelfTest | ( | XScuGic * | InstancePtr | ) |

Runs a self-test on the driver/device.

This test reads the ID registers and compares them.

Parameters

  InstancePtr | Pointer to the XScuGic instance.

Returns

          -XST_SUCCESS if self-test is successful.
          -XST_FAILURE if the self-test is not successful.

References XScuGic::IsReady, XScuGic_DistReadReg, XSCUGIC_PCELL_ID, and XSCUGIC_PCELLID_OFFSET.

Referenced by ScuGicExample().

void XScuGic_SetCpuID | ( | u32 | CpuCoreId | ) |

Updates the CpuId global variable.

Parameters

  CpuCoreId | CPU core number.

Returns
  None.

void XScuGic_SetPriorityTriggerType | ( | XScuGic * | InstancePtr,
|  | u32 | Int_Id,
|  | u8 | Priority,
|  | u8 | Trigger
| ) |  |

Sets the interrupt priority and trigger type for the specificd IRQ source.

Parameters

  InstancePtr | Pointer to the instance to be worked on.
  Int_Id | IRQ source number to modify.
  Priority | New priority for the IRQ source. 0 is highest priority, 0xF8(248) is lowest. There are 32 priority levels supported with a step of 8. Hence the supported priorities are 0, 8, 16, 32, 40 ..., 248.
  Trigger | New trigger type for the IRQ source. Each bit pair describes the configuration for an INT_ID. SFI Read Only b10 always PPI Read Only depending on how the PPIs are configured. b01 Active HIGH level sensitive b11 Rising edge sensitive SPI LSB is read only. b01 Active HIGH level sensitive b11 Rising edge sensitive/

Returns
  None.

References XScuGic::IsReady, XScuGic_DistReadReg, XScuGic_DistWriteReg, XSCUGIC_INT_CFG_MASK, XSCUGIC_INT_CFG_OFFSET_CALC, XSCUGIC_INTR_PRIO_MASK, XSCUGIC_MAX_INTR_PRIO_VAL, XSCUGIC_PRIORITY_MASK, XSCUGIC_PRIORITY_OFFSET_CALC, XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC, XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC, and XSCUGIC_SPI_INT_ID_START.

void XScuGic_SetPriTrigTypeByDistAddr | ( | UINTPTR | DistBaseAddress,
|  | u32 | Int_Id,
|  | u8 | Priority,
|  | u8 | Trigger
| ) |  |

Sets the interrupt priority and trigger type for the specificd IRQ source.

Parameters

  DistBaseAddress | Distributor base address
  Int_Id | IRQ source number to modify
  Priority | New priority for the IRQ source. 0 is highest priority, 0xF8(248) is lowest. There are 32 priority levels supported with a step of 8. Hence the supported priorities are 0, 8, 16, 32, 40 ..., 248.
  Trigger | New trigger type for the IRQ source. Each bit pair describes the configuration for an INT_ID. SFI Read Only b10 always PPI Read Only depending on how the PPIs are configured. b01 Active HIGH level sensitive b11 Rising edge sensitive SPI LSB is read only. b01 Active HIGH level sensitive b11 Rising edge sensitive/

Returns
  None.

Note
  This API has the similar functionality of XScuGic_SetPriority TriggerType() and should be used when there is no InstancePtr.

References XSCUGIC_INT_CFG_MASK, XSCUGIC_INT_CFG_OFFSET_CALC, XSCUGIC_INTR_PRIO_MASK, XSCUGIC_MAX_INTR_PRIO_VAL, XSCUGIC_PRIORITY_MASK, XSCUGIC_PRIORITY_OFFSET_CALC, XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC, XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC, XScuGic_ReadReg, XSCUGIC_SPI_INT_ID_START, and XScuGic_WriteReg.

s32 XScuGic_SoftwareIntr | ( | XScuGic * | InstancePtr,
|  | u32 | Int_Id,
|  | u32 | Cpu_Identifier
| ) |  |

Allows software to simulate an interrupt in the interrupt controller.

This function will only be successful when the interrupt controller has been started in simulation mode. A simulated interrupt allows the interrupt controller to be tested without any device to drive an interrupt input signal into it.

Parameters

  InstancePtr | Pointer to the XScuGic instance.
  Int_Id | Software interrupt ID to simulate an interrupt.
  Cpu_Identifier | List of CPUs to send the interrupt. For VERSAL_NET bits 0-7 specifies core ID to send the interrupt. bits 8-15 specifies the cluster id.

Returns

XST_SUCCESS if successful, or XST_FAILURE if the interrupt could not be simulated

References XScuGic::IsReady, XScuGic_DistWriteReg, XSCUGIC_SFI_TRIG_CPU_MASK, XSCUGIC_SFI_TRIG_INTID_MASK, and XSCUGIC_SFI_TRIG_OFFSET.

Referenced by ScuGicExample().

void XScuGic_Stop | ( | XScuGic * | InstancePtr | ) |

Checks if the interrupt target register contains all interrupts to be targeted for current CPU.

If they are programmed to be forwarded to current cpu, this API disable all interrupts and disable GIC distributor. This API also removes current CPU from interrupt target registers for all interrupt.

Parameters

  InstancePtr | Pointer to the instance to be worked on.

Returns
  None.

References XSCUGIC_DISABLE_OFFSET, XSCUGIC_DIST_EN_OFFSET, XScuGic_DistReadReg, XScuGic_DistWriteReg, XSCUGIC_EN_DIS_OFFSET_CALC, XSCUGIC_EN_INT_MASK, XSCUGIC_IROUTER_OFFSET_CALC, XSCUGIC_MAX_NUM_INTR_INPUTS, and XSCUGIC_SPI_TARGET_OFFSET_CALC.

Referenced by XScuGic_CfgInitialize().

void XScuGic_UnmapAllInterruptsFromCpu | ( | XScuGic * | InstancePtr,
|  | u8 | Cpu_Identifier
| ) |  |

Unmaps all SPI interrupts from the target CPU.

Parameters

  InstancePtr | Pointer to the instance to be worked on.
  Cpu_Identifier | CPU number from which the interrupts has to be unmapped.

Returns
  None.

References XScuGic_DistReadReg, XScuGic_DistWriteReg, XSCUGIC_MAX_NUM_INTR_INPUTS, and XSCUGIC_SPI_TARGET_OFFSET_CALC.

void XScuGic_UnmapAllInterruptsFromCpuByDistAddr | ( | UINTPTR | DistBaseAddress,
|  | u8 | Cpu_Id
| ) |  |

Unmaps all SPI interrupts from the target CPU.

Parameters

  DistBaseAddress | Device base address
  Cpu_Id | CPU number from which the interrupts has to be unmapped

Returns
  None.

References XSCUGIC_MAX_NUM_INTR_INPUTS, XScuGic_ReadReg, XSCUGIC_SPI_TARGET_OFFSET_CALC, and XScuGic_WriteReg.

## Variable Documentation

void* XScuGic_VectorTableEntry::CallBackRef

CallBackRef is the callback reference passed in by the upper layer when setting the Interrupt handler for specific interrupt ID, and it will passed back to Interrupt handler when it is invoked.

XScuGic_Config* XScuGic::Config

Configuration table entry.

Referenced by XScuGic_CfgInitialize(), XScuGic_Connect(), XScuGic_Disconnect(), and XScuGic_InterruptHandler().

UINTPTR XScuGic_Config::CpuBaseAddress

CPU Interface Register base address.

Referenced by ScuGicExample(), ScuGicInterruptSetup(), ScuGicSelfTestExample(), and SetupInterruptSystem().

u16 XScuGic_Config::DeviceId

Unique ID of device.

UINTPTR XScuGic_Config::DistBaseAddress

Distributor Register base address.

Referenced by XScuGic_CfgInitialize(), and XScuGic_IsInitialized().

Xil_InterruptHandler XScuGic_VectorTableEntry::Handler

Interrupt Handler.

XScuGic_VectorTableEntry XScuGic_Config::HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS]

Vector table of interrupt handlers.

Referenced by XScuGic_CfgInitialize(), XScuGic_Connect(), XScuGic_Disconnect(), XScuGic_InterruptHandler(), and XScuGic_RegisterHandler().

u32 XScuGic::IsReady

Device is initialized and ready.

Referenced by XScuGic_CfgInitialize(), XScuGic_Connect(), XScuGic_Disable(), XScuGic_Disconnect(), XScuGic_Enable(), XScuGic_GetPriorityTriggerType(), XScuGic_SelfTest(), XScuGic_SetPriorityTriggerType(), and XScuGic_SoftwareIntr().

u32 XScuGic::UnhandledInterrupts

Intc Statistics.

XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES]

Initial value:
= {
{
(u16)XPAR_SCUGIC_0_DEVICE_ID,
(u32)XPAR_SCUGIC_0_CPU_BASEADDR,
(u32)XPAR_SCUGIC_0_DIST_BASEADDR,
{{0}}
}
}

This table contains configuration information for each GIC device in the system.

Config table.

The XScuGic driver must know when to acknowledge the interrupt. The entry which specifies this as a bit mask where each bit corresponds to a specific interrupt. A bit set indicates to ACK it before servicing it. Generally, acknowledge before service is used when the interrupt signal is edge-sensitive, and after when the signal is level-sensitive.

Refer to the XScuGic_Config data structure in xscugic.h for details on how this table should be initialized.

Referenced by XScuGic_DeviceInitialize(), XScuGic_DeviceInterruptHandler(), XScuGic_LookupConfig(), and XScuGic_LookupConfigBaseAddr().

XScuGic_Config XScuGic_ConfigTable[]

Config table.

Config table.

The XScuGic driver must know when to acknowledge the interrupt. The entry which specifies this as a bit mask where each bit corresponds to a specific interrupt. A bit set indicates to ACK it before servicing it. Generally, acknowledge before service is used when the interrupt signal is edge-sensitive, and after when the signal is level-sensitive.

Refer to the XScuGic_Config data structure in xscugic.h for details on how this table should be initialized.

Referenced by XScuGic_DeviceInitialize(), XScuGic_DeviceInterruptHandler(), XScuGic_LookupConfig(), and XScuGic_LookupConfigBaseAddr().