| mipi_rx_phy Vitis Drivers API Documentation

- Overview
- Data Structures
- APIs
- File List
- Examples

Data Structures | Macros | Functions
Overview

## Data Structures
struct | XMipi_Rx_Phy_Config
| The configuration structure for mipi_rx_phy. More...
struct | XMipi_Rx_Phy
| The Xmipi_rx_phy Controller driver instance data. More...

## Macros
#define | XMIPI_RX_PHY_H_
| Prevent circular inclusions by using protection macros. More...
#define | XMIPI_RX_PHY_HW_H_
| Prevent circular inclusions by using protection macros. More...

## Functions
u32 | XMipi_Rx_Phy_CfgInitialize (XMipi_Rx_Phy *InstancePtr, XMipi_Rx_Phy_Config *CfgPtr, UINTPTR EffectiveAddr)
| Initialize the XMipi_Rx_Phy instance provided by the caller based on the given Config structure. More...
u32 | XMipi_Rx_Phy_Configure (XMipi_Rx_Phy *InstancePtr, u8 Handle, u32 Value)
| Configure the registers of the Mipi_Rx_Phy instance. More...
u8 | XMipi_Rx_Phy_GetRegIntfcPresent (XMipi_Rx_Phy *InstancePtr)
| Get if register interface is present from the config structure for specified Mipi_Rx_Phy instance. More...
u32 | XMipi_Rx_Phy_GetInfo (XMipi_Rx_Phy *InstancePtr, u8 Handle)
| Get information stored in the Mipi_Rx_Phy instance based on the handle passed. More...
void | XMipi_Rx_Phy_Reset (XMipi_Rx_Phy *InstancePtr)
| This is used to do a soft reset of the Mipi_Rx_Phy IP instance. More...
void | XMipi_Rx_Phy_ClearDataLane (XMipi_Rx_Phy *InstancePtr, u8 DataLane, u32 Mask)
| This is used to clear the Abort Error (Escape or High Speed) bits in the Data Lane 0 through 3. More...
u32 | XMipi_Rx_Phy_GetClkLaneStatus (XMipi_Rx_Phy *InstancePtr)
| This is used to get information about Clock Lane status. More...
u32 | XMipi_Rx_Phy_GetClkLaneMode (XMipi_Rx_Phy *InstancePtr)
| This is used to get specific Lane mode information about Clock Lane. More...
u32 | XMipi_Rx_Phy_GetDataLaneStatus (XMipi_Rx_Phy *InstancePtr, u8 DataLane)
| This is used to get information about a Data Lane status. More...
u8 | XMipi_Rx_Phy_GetDLCalibStatus (XMipi_Rx_Phy *InstancePtr, u8 DataLane)
| This is used to get Data Lane Calibration status. More...
u32 | XMipi_Rx_Phy_GetDataLaneMode (XMipi_Rx_Phy *InstancePtr, u8 DataLane)
| This is used to get specfic Lane mode information about a Data Lane. More...
u16 | XMipi_Rx_Phy_GetPacketCount (XMipi_Rx_Phy *InstancePtr, u8 DataLane)
| This is used to get count of packets received on each lane. More...
u32 | XMipi_Rx_Phy_GetVersionReg (XMipi_Rx_Phy *InstancePtr)
| This is used to get Mipi_Rx_Phy Version. More...
void | XMipi_Rx_Phy_Activate (XMipi_Rx_Phy *InstancePtr, u8 Flag)
| This function is used to enable or disable the Mipi_Rx_Phy core. More...
XMipi_Rx_Phy_Config * | XMipi_Rx_Phy_LookupConfig (UINTPTR BaseAddress)
| Look up the hardware configuration for a device instance. More...
u32 | XMipi_Rx_Phy_SelfTest (XMipi_Rx_Phy *InstancePtr)
| Runs a self-test on the driver/device. More...

## mipi_rx_phy Modes
#define | XMIPI_RX_PHY_MODE_MIN 0
| Lower limit for Mode. More...
#define | XMIPI_RX_PHY_LOW_POWER_MODE 0
| Lane in Low Power Mode. More...
#define | XMIPI_RX_PHY_HIGH_POWER_MODE 1
| Lane in High Power Mode. More...
#define | XMIPI_RX_PHY_ESCAPE_MODE 2
| Lane in Escape Mode. More...
#define | XMIPI_RX_PHY_MODE_MAX 2
| Upper Limit for mode. More...
#define | XMIPI_RX_PHY_MAX_LANES_V10 4
| V1.0 supports 4 Lanes. More...

## mipi_rx_phy Info Handles
#define | XMIPI_RX_PHY_HANDLE_MIN 0
| Lower Bound for XMIPI_RX_PHY_HANDLE. More...
#define | XMIPI_RX_PHY_HANDLE_IDELAY 0
| Handle for IDELAY Reg. More...
#define | XMIPI_RX_PHY_HANDLE_INIT_TIMER 1
| Handle for Initialization Timer. More...
#define | XMIPI_RX_PHY_HANDLE_WAKEUP 2
| Handle for Wakeup timer. More...
#define | XMIPI_RX_PHY_HANDLE_HSTIMEOUT 3
| Handle for HS Timeout. More...
#define | XMIPI_RX_PHY_HANDLE_ESCTIMEOUT 4
| Handle for Escape Timeout. More...
#define | XMIPI_RX_PHY_HANDLE_CLKLANE 5
| Handle for Clock Lane. More...
#define | XMIPI_RX_PHY_HANDLE_DLANE0 6
| Handle for Data Lane 0. More...
#define | XMIPI_RX_PHY_HANDLE_DLANE1 7
| Handle for Data Lane 1. More...
#define | XMIPI_RX_PHY_HANDLE_DLANE2 8
| Handle for Data Lane 2. More...
#define | XMIPI_RX_PHY_HANDLE_DLANE3 9
| Handle for Data Lane 3. More...
#define | XMIPI_RX_PHY_HANDLE_HSSETTLE0 10
| Handle for HS SETTLE L0. More...
#define | XMIPI_RX_PHY_HANDLE_HSSETTLE1 11
| Handle for HS SETTLE L1. More...
#define | XMIPI_RX_PHY_HANDLE_HSSETTLE2 12
| Handle for HS SETTLE L2. More...
#define | XMIPI_RX_PHY_HANDLE_HSSETTLE3 13
| Handle for HS SETTLE L3. More...
#define | XMIPI_RX_PHY_HANDLE_MAX 14
| Upper Bound for XMIPI_RX_PHY_HANDLE. More...

## mipi_rx_phy HSTIMEOUT range
#define | XMIPI_RX_PHY_HS_TIMEOUT_MIN_VALUE 10000UL
#define | XMIPI_RX_PHY_HS_TIMEOUT_MAX_VALUE 65541UL

## mipi_rx_phy HSSETTLE range
#define | XMIPI_RX_PHY_HS_SETTLE_MAX_VALUE 0x1FF

## mipi_rx_phy Flags to Enable or Disable core
#define | XMIPI_RX_PHY_ENABLE_FLAG 1
#define | XMIPI_RX_PHY_DISABLE_FLAG 0

## Device registers
Register sets of MIPI_RX_PHY
#define | XMIPI_RX_PHY_CTRL_REG_OFFSET 0x00000000
| Control Register. More...
#define | XMIPI_RX_PHY_VERSION_REG_OFFSET 0x00000004
| Core Version Register. More...
#define | XMIPI_RX_PHY_INIT_TIMER_REG_OFFSET 0x00000008
| Initialization Timer Register. More...
#define | XMIPI_RX_PHY_HSTIMEOUT_REG_OFFSET 0x00000010
| Watchdog timeout in HS mode Register. More...
#define | XMIPI_RX_PHY_ESCTIMEOUT_REG_OFFSET 0x00000014
| Goto Stop state on timeout timer Register. More...
#define | XMIPI_RX_PHY_CLSTATUS_REG_OFFSET 0x00000018
| Clk lane PHY error Status Register. More...
#define | XMIPI_RX_PHY_DL0STATUS_REG_OFFSET 0x0000001C
| Data lane 0 PHY error Status Register. More...
#define | XMIPI_RX_PHY_DL1STATUS_REG_OFFSET 0x00000020
| Data lane 1 PHY error Status Register. More...
#define | XMIPI_RX_PHY_DL2STATUS_REG_OFFSET 0x00000024
| Data lane 2 PHY error Status Register. More...
#define | XMIPI_RX_PHY_DL3STATUS_REG_OFFSET 0x00000028
| Data lane 3 PHY error Status Register. More...
#define | XMIPI_RX_PHY_HSSETTLE0_REG_OFFSET 0x00000030
| HS Settle Register L0. More...
#define | XMIPI_RX_PHY_HSSETTLE1_REG_OFFSET 0x00000048
| HS Settle Register L1. More...
#define | XMIPI_RX_PHY_HSSETTLE2_REG_OFFSET 0x0000004C
| HS Settle Register L2. More...
#define | XMIPI_RX_PHY_HSSETTLE3_REG_OFFSET 0x00000050
| HS Settle Register L3. More...

## Bitmasks and offsets of XMIPI_RX_PHY_CTRL_REG_OFFSET register
This register is used for the enabling/disabling and resetting the MIPI_RX_PHY
#define | XMIPI_RX_PHY_CTRL_REG_SOFTRESET_MASK 0x00000001
| Soft Reset. More...
#define | XMIPI_RX_PHY_CTRL_REG_PHYEN_MASK 0x00000002
| Enable/Disable controller. More...
#define | XMIPI_RX_PHY_CTRL_REG_SOFTRESET_OFFSET 0
| Bit offset for Soft Reset. More...
#define | XMIPI_RX_PHY_CTRL_REG_PHYEN_OFFSET 1
| Bit offset for PHY Enable. More...

## Bitmasks and offsets of XMIPI_RX_PHY_INIT_REG_OFFSET register
This register is used for lane Initialization. Recommended to use 1ms or longer in for TX mode and 200us-500us for RX mode
#define | XMIPI_RX_PHY_INIT_REG_VAL_MASK 0xFFFFFFFF
| Init Timer value in ns. More...
#define | XMIPI_RX_PHY_INIT_REG_VAL_OFFSET 0
| Bit offset for Init Timer. More...

## Bitmask and offset of XMIPI_RX_PHY_HSTIMEOUT_REG_OFFSET register
This register is used to program watchdog timer in high speed mode. Default value is 65541. Valid range 1000-65541.
#define | XMIPI_RX_PHY_HSTIMEOUT_REG_TIMEOUT_MASK 0xFFFFFFFF
| HS_RX_TIMEOUT Received. More...
#define | XMIPI_RX_PHY_HSTIMEOUT_REG_TIMEOUT_OFFSET 0
| Bit offset for Timeout. More...

## Bitmask and offset of XMIPI_RX_PHY_ESCTIMEOUT_REG_OFFSET register
This register contains Rx Data Lanes timeout for watchdog timer in escape mode.
#define | XMIPI_RX_PHY_ESCTIMEOUT_REG_VAL_MASK 0xFFFFFFFF
| Escape Timout Value. More...
#define | XMIPI_RX_PHY_ESCTIMEOUT_REG_VAL_OFFSET 0
| Bit offset for Escape Timeout. More...

## Bitmask and offset of XMIPI_RX_PHY_CLSTATUS_REG_OFFSET register
This register contains the clock lane status and state machine control.
#define | XMIPI_RX_PHY_CLSTATUS_REG_ERRCTRL_MASK 0x00000020
| Clock lane control error. More...
#define | XMIPI_RX_PHY_CLSTATUS_REG_STOPSTATE_MASK 0x00000010
| Clock lane stop state. More...
#define | XMIPI_RX_PHY_CLSTATUS_REG_INITDONE_MASK 0x00000008
| Initialization done bit. More...
#define | XMIPI_RX_PHY_CLSTATUS_REG_ULPS_MASK 0x00000004
| Set in ULPS mode. More...
#define | XMIPI_RX_PHY_CLSTATUS_REG_MODE_MASK 0x00000003
| Low, High, Esc mode. More...
#define | XMIPI_RX_PHY_CLSTATUS_ALLMASK
#define | XMIPI_RX_PHY_CLSTATUS_REG_ERRCTRL_OFFSET 5
| Bit offset for Control Error on Clock. More...
#define | XMIPI_RX_PHY_CLSTATUS_REG_STOPSTATE_OFFSET 4
| Bit offset for Stop State on Clock. More...
#define | XMIPI_RX_PHY_CLSTATUS_REG_INITDONE_OFFSET 3
| Bit offset for Initialization Done. More...
#define | XMIPI_RX_PHY_CLSTATUS_REG_ULPS_OFFSET 2
| Bit offset for ULPS. More...
#define | XMIPI_RX_PHY_CLSTATUS_REG_MODE_OFFSET 0
| Bit offset for Mode bits. More...

## Bitmasks and offsets of XMIPI_RX_PHY_DLxSTATUS_REG_OFFSET register
This register contains the data lanes status
#define | XMIPI_RX_PHY_DLXSTATUS_REG_PACKETCOUNT_MASK 0xFFFF0000
| Packet Count. More...
#define | XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_STATUS_MASK 0x00000100
| Calib status. More...
#define | XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_COMPLETE_MASK 0x00000080
| Calib complete. More...
#define | XMIPI_RX_PHY_DLXSTATUS_REG_STOP_MASK 0x00000040
| Stop State on data lane. More...
#define | XMIPI_RX_PHY_DLXSTATUS_REG_ESCABRT_MASK 0x00000020
| Set on Data Lane Esc timeout occurs. More...
#define | XMIPI_RX_PHY_DLXSTATUS_REG_HSABRT_MASK 0x00000010
| Set on Data Lane HS timeout. More...
#define | XMIPI_RX_PHY_DLXSTATUS_REG_INITDONE_MASK 0x00000008
| Set after initialization. More...
#define | XMIPI_RX_PHY_DLXSTATUS_REG_ULPS_MASK 0x00000004
| Set when MIPI_RX_PHY in ULPS mode. More...
#define | XMIPI_RX_PHY_DLXSTATUS_REG_MODE_MASK 0x00000003
| Control Mode (Esc, Low, High) of Data Lane. More...
#define | XMIPI_RX_PHY_DLXSTATUS_ALLMASK
#define | XMIPI_RX_PHY_DLXSTATUS_REG_PACKCOUNT_OFFSET 16
| Bit offset packet count. More...
#define | XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_STATUS_OFFSET 8
| Bit offset calib status. More...
#define | XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_COMPLETE_OFFSET 7
| Bit offset Calib complete. More...
#define | XMIPI_RX_PHY_DLXSTATUS_REG_STOP_OFFSET 6
| Bit offset for Stop State. More...
#define | XMIPI_RX_PHY_DLXSTATUS_REG_ESCABRT_OFFSET 5
| Bit offset for Escape Abort. More...
#define | XMIPI_RX_PHY_DLXSTATUS_REG_HSABRT_OFFSET 4
| Bit offset for High Speed Abort. More...
#define | XMIPI_RX_PHY_DLXSTATUS_REG_INITDONE_OFFSET 3
| Bit offset for Initialization done. More...
#define | XMIPI_RX_PHY_DLXSTATUS_REG_ULPS_OFFSET 2
| Bit offset for ULPS. More...
#define | XMIPI_RX_PHY_DLXSTATUS_REG_MODE_OFFSET 0
| Bit offset for Modes. More...

## Bitmask and offset of XMIPI_RX_PHY_HSSETTLE_REG_OFFSET register
This register is used to program the HS SETTLE register. Default value is 135 + 10UI.
#define | XMIPI_RX_PHY_HSSETTLE_REG_TIMEOUT_MASK 0x1FF
| HS_SETTLE value. More...
#define | XMIPI_RX_PHY_HSSETTLE_REG_TIMEOUT_OFFSET 0
| Bit offset for HS_SETTLE. More...

## Macro Definition Documentation

#define XMIPI_RX_PHY_CLSTATUS_REG_ERRCTRL_MASK 0x00000020

Clock lane control error.

Only for RX

#define XMIPI_RX_PHY_CLSTATUS_REG_ERRCTRL_OFFSET 5

Bit offset for Control Error on Clock.

#define XMIPI_RX_PHY_CLSTATUS_REG_INITDONE_MASK 0x00000008

Initialization done bit.

#define XMIPI_RX_PHY_CLSTATUS_REG_INITDONE_OFFSET 3

Bit offset for Initialization Done.

#define XMIPI_RX_PHY_CLSTATUS_REG_MODE_MASK 0x00000003

Low, High, Esc mode.

Referenced by XMipi_Rx_Phy_GetClkLaneMode().

#define XMIPI_RX_PHY_CLSTATUS_REG_MODE_OFFSET 0

Bit offset for Mode bits.

#define XMIPI_RX_PHY_CLSTATUS_REG_OFFSET 0x00000018

Clk lane PHY error Status Register.

Referenced by XMipi_Rx_Phy_GetClkLaneStatus(), and XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_CLSTATUS_REG_STOPSTATE_MASK 0x00000010

Clock lane stop state.

#define XMIPI_RX_PHY_CLSTATUS_REG_STOPSTATE_OFFSET 4

Bit offset for Stop State on Clock.

#define XMIPI_RX_PHY_CLSTATUS_REG_ULPS_MASK 0x00000004

Set in ULPS mode.

#define XMIPI_RX_PHY_CLSTATUS_REG_ULPS_OFFSET 2

Bit offset for ULPS.

#define XMIPI_RX_PHY_CTRL_REG_OFFSET 0x00000000

Control Register.

Referenced by XMipi_Rx_Phy_Activate(), and XMipi_Rx_Phy_Reset().

#define XMIPI_RX_PHY_CTRL_REG_PHYEN_MASK 0x00000002

Enable/Disable controller.

Referenced by XMipi_Rx_Phy_Activate().

#define XMIPI_RX_PHY_CTRL_REG_PHYEN_OFFSET 1

Bit offset for PHY Enable.

#define XMIPI_RX_PHY_CTRL_REG_SOFTRESET_MASK 0x00000001

Soft Reset.

Referenced by XMipi_Rx_Phy_Reset().

#define XMIPI_RX_PHY_CTRL_REG_SOFTRESET_OFFSET 0

Bit offset for Soft Reset.

#define XMIPI_RX_PHY_DL0STATUS_REG_OFFSET 0x0000001C

Data lane 0 PHY error Status Register.

Referenced by XMipi_Rx_Phy_ClearDataLane(), XMipi_Rx_Phy_GetDataLaneStatus(), XMipi_Rx_Phy_GetDLCalibStatus(), XMipi_Rx_Phy_GetInfo(), and XMipi_Rx_Phy_GetPacketCount().

#define XMIPI_RX_PHY_DL1STATUS_REG_OFFSET 0x00000020

Data lane 1 PHY error Status Register.

Referenced by XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_DL2STATUS_REG_OFFSET 0x00000024

Data lane 2 PHY error Status Register.

Referenced by XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_DL3STATUS_REG_OFFSET 0x00000028

Data lane 3 PHY error Status Register.

Referenced by XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_COMPLETE_MASK 0x00000080

Calib complete.

Referenced by XMipi_Rx_Phy_GetDLCalibStatus().

#define XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_COMPLETE_OFFSET 7

Bit offset Calib complete.

#define XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_STATUS_MASK 0x00000100

Calib status.

Referenced by XMipi_Rx_Phy_GetDLCalibStatus().

#define XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_STATUS_OFFSET 8

Bit offset calib status.

#define XMIPI_RX_PHY_DLXSTATUS_REG_ESCABRT_MASK 0x00000020

Set on Data Lane Esc timeout occurs.

Referenced by XMipi_Rx_Phy_ClearDataLane().

#define XMIPI_RX_PHY_DLXSTATUS_REG_ESCABRT_OFFSET 5

Bit offset for Escape Abort.

#define XMIPI_RX_PHY_DLXSTATUS_REG_HSABRT_MASK 0x00000010

Set on Data Lane HS timeout.

Referenced by XMipi_Rx_Phy_ClearDataLane().

#define XMIPI_RX_PHY_DLXSTATUS_REG_HSABRT_OFFSET 4

Bit offset for High Speed Abort.

#define XMIPI_RX_PHY_DLXSTATUS_REG_INITDONE_MASK 0x00000008

Set after initialization.

#define XMIPI_RX_PHY_DLXSTATUS_REG_INITDONE_OFFSET 3

Bit offset for Initialization done.

#define XMIPI_RX_PHY_DLXSTATUS_REG_MODE_MASK 0x00000003

Control Mode (Esc, Low, High) of Data Lane.

Referenced by XMipi_Rx_Phy_GetDataLaneMode().

#define XMIPI_RX_PHY_DLXSTATUS_REG_MODE_OFFSET 0

Bit offset for Modes.

#define XMIPI_RX_PHY_DLXSTATUS_REG_PACKCOUNT_OFFSET 16

Bit offset packet count.

Referenced by XMipi_Rx_Phy_GetPacketCount().

#define XMIPI_RX_PHY_DLXSTATUS_REG_PACKETCOUNT_MASK 0xFFFF0000

Packet Count.

Referenced by XMipi_Rx_Phy_GetPacketCount().

#define XMIPI_RX_PHY_DLXSTATUS_REG_STOP_MASK 0x00000040

Stop State on data lane.

#define XMIPI_RX_PHY_DLXSTATUS_REG_STOP_OFFSET 6

Bit offset for Stop State.

#define XMIPI_RX_PHY_DLXSTATUS_REG_ULPS_MASK 0x00000004

Set when MIPI_RX_PHY in ULPS mode.

#define XMIPI_RX_PHY_DLXSTATUS_REG_ULPS_OFFSET 2

Bit offset for ULPS.

#define XMIPI_RX_PHY_ESCAPE_MODE 2

Lane in Escape Mode.

#define XMIPI_RX_PHY_ESCTIMEOUT_REG_OFFSET 0x00000014

Goto Stop state on timeout timer Register.

Referenced by XMipi_Rx_Phy_Configure(), and XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_ESCTIMEOUT_REG_VAL_MASK 0xFFFFFFFF

Escape Timout Value.

#define XMIPI_RX_PHY_ESCTIMEOUT_REG_VAL_OFFSET 0

Bit offset for Escape Timeout.

#define XMIPI_RX_PHY_H_

Prevent circular inclusions by using protection macros.

#define XMIPI_RX_PHY_HANDLE_CLKLANE 5

Handle for Clock Lane.

Referenced by XMipi_Rx_Phy_Configure(), and XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_HANDLE_DLANE0 6

Handle for Data Lane 0.

Referenced by XMipi_Rx_Phy_Configure(), and XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_HANDLE_DLANE1 7

Handle for Data Lane 1.

Referenced by XMipi_Rx_Phy_Configure(), and XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_HANDLE_DLANE2 8

Handle for Data Lane 2.

Referenced by XMipi_Rx_Phy_Configure(), and XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_HANDLE_DLANE3 9

Handle for Data Lane 3.

Referenced by XMipi_Rx_Phy_Configure(), and XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_HANDLE_ESCTIMEOUT 4

Handle for Escape Timeout.

Referenced by XMipi_Rx_Phy_Configure(), and XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_HANDLE_HSSETTLE0 10

Handle for HS SETTLE L0.

Referenced by XMipi_Rx_Phy_Configure(), and XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_HANDLE_HSSETTLE1 11

Handle for HS SETTLE L1.

Referenced by XMipi_Rx_Phy_Configure(), and XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_HANDLE_HSSETTLE2 12

Handle for HS SETTLE L2.

Referenced by XMipi_Rx_Phy_Configure(), and XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_HANDLE_HSSETTLE3 13

Handle for HS SETTLE L3.

Referenced by XMipi_Rx_Phy_Configure(), and XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_HANDLE_HSTIMEOUT 3

Handle for HS Timeout.

Referenced by XMipi_Rx_Phy_Configure(), XMipi_Rx_Phy_GetInfo(), and XMipi_Rx_Phy_SelfTest().

#define XMIPI_RX_PHY_HANDLE_IDELAY 0

Handle for IDELAY Reg.

#define XMIPI_RX_PHY_HANDLE_INIT_TIMER 1

Handle for Initialization Timer.

Referenced by XMipi_Rx_Phy_Configure(), and XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_HANDLE_MAX 14

Upper Bound for XMIPI_RX_PHY_HANDLE.

Referenced by XMipi_Rx_Phy_Configure(), and XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_HANDLE_MIN 0

Lower Bound for XMIPI_RX_PHY_HANDLE.

#define XMIPI_RX_PHY_HANDLE_WAKEUP 2

Handle for Wakeup timer.

#define XMIPI_RX_PHY_HIGH_POWER_MODE 1

Lane in High Power Mode.

#define XMIPI_RX_PHY_HSSETTLE0_REG_OFFSET 0x00000030

HS Settle Register L0.

Referenced by XMipi_Rx_Phy_Configure(), and XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_HSSETTLE1_REG_OFFSET 0x00000048

HS Settle Register L1.

Referenced by XMipi_Rx_Phy_Configure(), and XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_HSSETTLE2_REG_OFFSET 0x0000004C

HS Settle Register L2.

Referenced by XMipi_Rx_Phy_Configure(), and XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_HSSETTLE3_REG_OFFSET 0x00000050

HS Settle Register L3.

Referenced by XMipi_Rx_Phy_Configure(), and XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_HSSETTLE_REG_TIMEOUT_MASK 0x1FF

HS_SETTLE value.

#define XMIPI_RX_PHY_HSSETTLE_REG_TIMEOUT_OFFSET 0

Bit offset for HS_SETTLE.

#define XMIPI_RX_PHY_HSTIMEOUT_REG_OFFSET 0x00000010

Watchdog timeout in HS mode Register.

Referenced by XMipi_Rx_Phy_Configure(), and XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_HSTIMEOUT_REG_TIMEOUT_MASK 0xFFFFFFFF

HS_RX_TIMEOUT Received.

#define XMIPI_RX_PHY_HSTIMEOUT_REG_TIMEOUT_OFFSET 0

Bit offset for Timeout.

#define XMIPI_RX_PHY_HW_H_

Prevent circular inclusions by using protection macros.

#define XMIPI_RX_PHY_INIT_REG_VAL_MASK 0xFFFFFFFF

Init Timer value in ns.

#define XMIPI_RX_PHY_INIT_REG_VAL_OFFSET 0

Bit offset for Init Timer.

#define XMIPI_RX_PHY_INIT_TIMER_REG_OFFSET 0x00000008

Initialization Timer Register.

Referenced by XMipi_Rx_Phy_Configure(), and XMipi_Rx_Phy_GetInfo().

#define XMIPI_RX_PHY_LOW_POWER_MODE 0

Lane in Low Power Mode.

#define XMIPI_RX_PHY_MAX_LANES_V10 4

V1.0 supports 4 Lanes.

#define XMIPI_RX_PHY_MODE_MAX 2

Upper Limit for mode.

#define XMIPI_RX_PHY_MODE_MIN 0

Lower limit for Mode.

#define XMIPI_RX_PHY_VERSION_REG_OFFSET 0x00000004

Core Version Register.

Referenced by XMipi_Rx_Phy_GetVersionReg().

## Function Documentation

void XMipi_Rx_Phy_Activate | ( | XMipi_Rx_Phy * | InstancePtr,
|  | u8 | Flag
| ) |  |

This function is used to enable or disable the Mipi_Rx_Phy core.

Parameters

  InstancePtr | is the XMipi_Rx_Phy instance to operate on.
  Flag | denoting whether to enable or disable the Mipi_Rx_Phy core

Returns
  None.

Note
  None.

References XMipi_Rx_Phy_Config::BaseAddr, XMipi_Rx_Phy::Config, XMipi_Rx_Phy_Config::IsRegisterPresent, XMIPI_RX_PHY_CTRL_REG_OFFSET, and XMIPI_RX_PHY_CTRL_REG_PHYEN_MASK.

u32 XMipi_Rx_Phy_CfgInitialize | ( | XMipi_Rx_Phy * | InstancePtr,
|  | XMipi_Rx_Phy_Config * | CfgPtr,
|  | UINTPTR | EffectiveAddr
| ) |  |

Initialize the XMipi_Rx_Phy instance provided by the caller based on the given Config structure.

Parameters

  InstancePtr | is the XMipi_Rx_Phy instance to operate on.
  CfgPtr | is the device configuration structure containing information about a specific Mipi_Rx_Phy instance.
  EffectiveAddr | is the base address of the device. If address translation is being used, then this parameter must reflect the virtual base address. Otherwise, the physical address should be used.

Returns
  - XST_SUCCESS Initialization was successful.

Note
  None.

References XMipi_Rx_Phy_Config::BaseAddr, XMipi_Rx_Phy::Config, and XMipi_Rx_Phy::IsReady.

Referenced by Mipi_Rx_PhySelfTestExample().

void XMipi_Rx_Phy_ClearDataLane | ( | XMipi_Rx_Phy * | InstancePtr,
|  | u8 | DataLane,
|  | u32 | Mask
| ) |  |

This is used to clear the Abort Error (Escape or High Speed) bits in the Data Lane 0 through 3.

Parameters

  InstancePtr | is the XMipi_Rx_Phy instance to operate on.
  DataLane | represents which Data Lane to act upon
  Mask | contains information about which bits to reset

Returns
  None

Note
  None.

References XMipi_Rx_Phy_Config::BaseAddr, XMipi_Rx_Phy::Config, XMipi_Rx_Phy_Config::IsRegisterPresent, XMIPI_RX_PHY_DL0STATUS_REG_OFFSET, XMIPI_RX_PHY_DLXSTATUS_REG_ESCABRT_MASK, and XMIPI_RX_PHY_DLXSTATUS_REG_HSABRT_MASK.

u32 XMipi_Rx_Phy_Configure | ( | XMipi_Rx_Phy * | InstancePtr,
|  | u8 | Handle,
|  | u32 | Value
| ) |  |

Configure the registers of the Mipi_Rx_Phy instance.

Parameters

  InstancePtr | is the XMipi_Rx_Phy instance to operate on.
  Handle | to one of the registers to be configured
  Value | to be set for the particular Handle of the Mipi_Rx_Phy instance

Returns
  - XST_SUCCESS on successful register update.
  - XST_FAILURE If incorrect handle was passed

Note
  There is a limit on the minimum and maximum values of the HS Timeout register.

References XMipi_Rx_Phy::Config, XMipi_Rx_Phy_Config::EnableTimeOutRegs, XMipi_Rx_Phy_Config::IsDphy, XMipi_Rx_Phy_Config::IsRegisterPresent, XMIPI_RX_PHY_ESCTIMEOUT_REG_OFFSET, XMIPI_RX_PHY_HANDLE_CLKLANE, XMIPI_RX_PHY_HANDLE_DLANE0, XMIPI_RX_PHY_HANDLE_DLANE1, XMIPI_RX_PHY_HANDLE_DLANE2, XMIPI_RX_PHY_HANDLE_DLANE3, XMIPI_RX_PHY_HANDLE_ESCTIMEOUT, XMIPI_RX_PHY_HANDLE_HSSETTLE0, XMIPI_RX_PHY_HANDLE_HSSETTLE1, XMIPI_RX_PHY_HANDLE_HSSETTLE2, XMIPI_RX_PHY_HANDLE_HSSETTLE3, XMIPI_RX_PHY_HANDLE_HSTIMEOUT, XMIPI_RX_PHY_HANDLE_INIT_TIMER, XMIPI_RX_PHY_HANDLE_MAX, XMIPI_RX_PHY_HSSETTLE0_REG_OFFSET, XMIPI_RX_PHY_HSSETTLE1_REG_OFFSET, XMIPI_RX_PHY_HSSETTLE2_REG_OFFSET, XMIPI_RX_PHY_HSSETTLE3_REG_OFFSET, XMIPI_RX_PHY_HSTIMEOUT_REG_OFFSET, and XMIPI_RX_PHY_INIT_TIMER_REG_OFFSET.

u32 XMipi_Rx_Phy_GetClkLaneMode | ( | XMipi_Rx_Phy * | InstancePtr | ) |

This is used to get specific Lane mode information about Clock Lane.

Parameters

  InstancePtr | is the XMipi_Rx_Phy instance to operate on.

Returns
  Bitmask containing mode in which the Clock Lane in Mipi_Rx_Phy is in.

Note
  None.

References XMipi_Rx_Phy::Config, XMipi_Rx_Phy_Config::IsDphy, XMipi_Rx_Phy_Config::IsRegisterPresent, XMIPI_RX_PHY_CLSTATUS_REG_MODE_MASK, and XMipi_Rx_Phy_GetClkLaneStatus().

u32 XMipi_Rx_Phy_GetClkLaneStatus | ( | XMipi_Rx_Phy * | InstancePtr | ) |

This is used to get information about Clock Lane status.

Parameters

  InstancePtr | is the XMipi_Rx_Phy instance to operate on.

Returns
  Bitmask containing which of the events have occured along with the mode of the Clock Lane in Phy

Note
  None.

References XMipi_Rx_Phy_Config::BaseAddr, XMipi_Rx_Phy::Config, XMipi_Rx_Phy_Config::IsDphy, XMipi_Rx_Phy_Config::IsRegisterPresent, and XMIPI_RX_PHY_CLSTATUS_REG_OFFSET.

Referenced by XMipi_Rx_Phy_GetClkLaneMode().

u32 XMipi_Rx_Phy_GetDataLaneMode | ( | XMipi_Rx_Phy * | InstancePtr,
|  | u8 | DataLane
| ) |  |

This is used to get specfic Lane mode information about a Data Lane.

Parameters

  InstancePtr | is the XMipi_Rx_Phy instance to operate on.
  DataLane | for which the mode info is requested.

Returns
  Bitmask containing mode in which the Data Lane in Mipi_Rx_Phy is in.

Note
  None.

References XMipi_Rx_Phy::Config, XMipi_Rx_Phy_Config::IsRegisterPresent, XMIPI_RX_PHY_DLXSTATUS_REG_MODE_MASK, and XMipi_Rx_Phy_GetDataLaneStatus().

u32 XMipi_Rx_Phy_GetDataLaneStatus | ( | XMipi_Rx_Phy * | InstancePtr,
|  | u8 | DataLane
| ) |  |

This is used to get information about a Data Lane status.

Parameters

  InstancePtr | is the XMipi_Rx_Phy instance to operate on.
  DataLane | for which the status is sought for.

Returns
  Bitmask containing which of the events have occured along with the mode of the Data Lane in Phy

Note
  None.

References XMipi_Rx_Phy_Config::BaseAddr, XMipi_Rx_Phy::Config, XMipi_Rx_Phy_Config::IsRegisterPresent, and XMIPI_RX_PHY_DL0STATUS_REG_OFFSET.

Referenced by XMipi_Rx_Phy_GetDataLaneMode().

u8 XMipi_Rx_Phy_GetDLCalibStatus | ( | XMipi_Rx_Phy * | InstancePtr,
|  | u8 | DataLane
| ) |  |

This is used to get Data Lane Calibration status.

Parameters

  InstancePtr | is the XMipi_Rx_Phy instance to operate on.
  DataLane | for which the calib status is sought for.

Returns
  XST_SUCCESS - Calibration Complete, Calibration packet received XST_NO_DATA - Calibration Complete, Calibration packet is not received XST_FAILURE - Calibration failed

Note
  None.

References XMipi_Rx_Phy_Config::BaseAddr, XMipi_Rx_Phy::Config, XMipi_Rx_Phy_Config::IsRegisterPresent, XMIPI_RX_PHY_DL0STATUS_REG_OFFSET, XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_COMPLETE_MASK, and XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_STATUS_MASK.

u32 XMipi_Rx_Phy_GetInfo | ( | XMipi_Rx_Phy * | InstancePtr,
|  | u8 | Handle
| ) |  |

Get information stored in the Mipi_Rx_Phy instance based on the handle passed.

Parameters

  InstancePtr | is the XMipi_Rx_Phy instance to operate on.
  Handle | to one of the registers to be configured

Returns
  The value stored in the corresponding register

Note
  None.

References XMipi_Rx_Phy::Config, XMipi_Rx_Phy_Config::EnableTimeOutRegs, XMipi_Rx_Phy_Config::EscTimeout, XMipi_Rx_Phy_Config::HSTimeOut, XMipi_Rx_Phy_Config::IsDphy, XMipi_Rx_Phy_Config::IsRegisterPresent, XMipi_Rx_Phy_Config::MaxLanesPresent, XMIPI_RX_PHY_CLSTATUS_REG_OFFSET, XMIPI_RX_PHY_DL0STATUS_REG_OFFSET, XMIPI_RX_PHY_DL1STATUS_REG_OFFSET, XMIPI_RX_PHY_DL2STATUS_REG_OFFSET, XMIPI_RX_PHY_DL3STATUS_REG_OFFSET, XMIPI_RX_PHY_ESCTIMEOUT_REG_OFFSET, XMIPI_RX_PHY_HANDLE_CLKLANE, XMIPI_RX_PHY_HANDLE_DLANE0, XMIPI_RX_PHY_HANDLE_DLANE1, XMIPI_RX_PHY_HANDLE_DLANE2, XMIPI_RX_PHY_HANDLE_DLANE3, XMIPI_RX_PHY_HANDLE_ESCTIMEOUT, XMIPI_RX_PHY_HANDLE_HSSETTLE0, XMIPI_RX_PHY_HANDLE_HSSETTLE1, XMIPI_RX_PHY_HANDLE_HSSETTLE2, XMIPI_RX_PHY_HANDLE_HSSETTLE3, XMIPI_RX_PHY_HANDLE_HSTIMEOUT, XMIPI_RX_PHY_HANDLE_INIT_TIMER, XMIPI_RX_PHY_HANDLE_MAX, XMIPI_RX_PHY_HSSETTLE0_REG_OFFSET, XMIPI_RX_PHY_HSSETTLE1_REG_OFFSET, XMIPI_RX_PHY_HSSETTLE2_REG_OFFSET, XMIPI_RX_PHY_HSSETTLE3_REG_OFFSET, XMIPI_RX_PHY_HSTIMEOUT_REG_OFFSET, and XMIPI_RX_PHY_INIT_TIMER_REG_OFFSET.

Referenced by XMipi_Rx_Phy_SelfTest().

u16 XMipi_Rx_Phy_GetPacketCount | ( | XMipi_Rx_Phy * | InstancePtr,
|  | u8 | DataLane
| ) |  |

This is used to get count of packets received on each lane.

Parameters

  InstancePtr | is the XMipi_Rx_Phy instance to operate on.
  DataLane | for which the mode info is requested.

Returns
  Bitmask containing mode in which the Data Lane in Mipi_Rx_Phy is in.

Note
  None.

References XMipi_Rx_Phy_Config::BaseAddr, XMipi_Rx_Phy::Config, XMipi_Rx_Phy_Config::IsRegisterPresent, XMIPI_RX_PHY_DL0STATUS_REG_OFFSET, XMIPI_RX_PHY_DLXSTATUS_REG_PACKCOUNT_OFFSET, and XMIPI_RX_PHY_DLXSTATUS_REG_PACKETCOUNT_MASK.

u8 XMipi_Rx_Phy_GetRegIntfcPresent | ( | XMipi_Rx_Phy * | InstancePtr | ) |

Get if register interface is present from the config structure for specified Mipi_Rx_Phy instance.

Parameters

  InstancePtr | is the XMipi_Rx_Phy instance to operate on.

Returns
  - 1 if register interface is present
  - 0 if register interface is absent

Note
  None.

References XMipi_Rx_Phy::Config, and XMipi_Rx_Phy_Config::IsRegisterPresent.

Referenced by Mipi_Rx_PhySelfTestExample().

u32 XMipi_Rx_Phy_GetVersionReg | ( | XMipi_Rx_Phy * | InstancePtr | ) |

This is used to get Mipi_Rx_Phy Version.

Parameters

  InstancePtr | is the XMipi_Rx_Phy instance to operate on.

Returns
  Returns major and minor Version number of this Mipi_Rx_Phy IP

Note
  None.

References XMipi_Rx_Phy_Config::BaseAddr, XMipi_Rx_Phy::Config, XMipi_Rx_Phy_Config::IsRegisterPresent, and XMIPI_RX_PHY_VERSION_REG_OFFSET.

XMipi_Rx_Phy_Config * XMipi_Rx_Phy_LookupConfig | ( | UINTPTR | BaseAddress | ) |

Look up the hardware configuration for a device instance.

Parameters

  BaseAddress | is the BaseAddress of the device to lookup for

Returns
  The reference to the configuration record in the configuration table (in xmipi_rx_phy_g.c) corresponding to the BaseAddr or if not found,a NULL pointer is returned.

Note
  None

Referenced by Mipi_Rx_PhySelfTestExample().

void XMipi_Rx_Phy_Reset | ( | XMipi_Rx_Phy * | InstancePtr | ) |

This is used to do a soft reset of the Mipi_Rx_Phy IP instance.

The reset takes approx 20 core clock cycles to become effective.

Parameters

  InstancePtr | is the XMipi_Rx_Phy instance to operate on.

Returns
  None

Note
  None.

References XMipi_Rx_Phy::Config, XMipi_Rx_Phy::IsReady, XMipi_Rx_Phy_Config::IsRegisterPresent, XMIPI_RX_PHY_CTRL_REG_OFFSET, and XMIPI_RX_PHY_CTRL_REG_SOFTRESET_MASK.

u32 XMipi_Rx_Phy_SelfTest | ( | XMipi_Rx_Phy * | InstancePtr | ) |

Runs a self-test on the driver/device.

This test checks if HS Timeout value present in register matches the one from the generated file.

Parameters

  InstancePtr | is a pointer to the XMipi_Rx_Phy instance.

Returns
  - XST_SUCCESS if self-test was successful

- XST_FAILURE if the read value was not equal to _g.c file

Note
  None.

References XMipi_Rx_Phy::Config, XMipi_Rx_Phy_Config::HSTimeOut, XMipi_Rx_Phy_GetInfo(), and XMIPI_RX_PHY_HANDLE_HSTIMEOUT.

Referenced by Mipi_Rx_PhySelfTestExample().