| can Vitis Drivers API Documentation

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Macros
xcan_l.h File Reference

## Macros
#define | XCAN_L_H
| by using protection macros More...
#define | XCan_ReadReg(BaseAddress, RegOffset) Xil_In32((BaseAddress) + (RegOffset))
| This macro reads the given register. More...
#define | XCan_WriteReg(BaseAddress, RegOffset, Data) Xil_Out32((BaseAddress) + (RegOffset), (Data))
| This macro writes the given register. More...
Register offsets for the CAN. Each register is 32 bits.
#define | XCAN_SRR_OFFSET 0x000
| Software Reset Register. More...
#define | XCAN_MSR_OFFSET 0x004
| Mode Select Register. More...
#define | XCAN_BRPR_OFFSET 0x008
| Baud Rate Prescaler Register. More...
#define | XCAN_BTR_OFFSET 0x00C
| Bit Timing Register. More...
#define | XCAN_ECR_OFFSET 0x010
| Error Counter Register. More...
#define | XCAN_ESR_OFFSET 0x014
| Error Status Register. More...
#define | XCAN_SR_OFFSET 0x018
| Status Register. More...
#define | XCAN_ISR_OFFSET 0x01C
| Interrupt Status Register. More...
#define | XCAN_IER_OFFSET 0x020
| Interrupt Enable Register. More...
#define | XCAN_ICR_OFFSET 0x024
| Interrupt Clear Register. More...
#define | XCAN_TXFIFO_ID_OFFSET 0x030
| TX FIFO ID. More...
#define | XCAN_TXFIFO_DLC_OFFSET 0x034
| TX FIFO DLC. More...
#define | XCAN_TXFIFO_DW1_OFFSET 0x038
| TX FIFO Data Word 1. More...
#define | XCAN_TXFIFO_DW2_OFFSET 0x03C
| TX FIFO Data Word 2. More...
#define | XCAN_TXBUF_ID_OFFSET 0x040
| TX High Priority Buffer ID. More...
#define | XCAN_TXBUF_DLC_OFFSET 0x044
| TX High Priority Buffer DLC. More...
#define | XCAN_TXBUF_DW1_OFFSET 0x048
| TX High Priority Buf Data Word 1. More...
#define | XCAN_TXBUF_DW2_OFFSET 0x04C
| TX High Priority Buf Data Word 2. More...
#define | XCAN_RXFIFO_ID_OFFSET 0x050
| RX FIFO ID. More...
#define | XCAN_RXFIFO_DLC_OFFSET 0x054
| RX FIFO DLC. More...
#define | XCAN_RXFIFO_DW1_OFFSET 0x058
| RX FIFO Data Word 1. More...
#define | XCAN_RXFIFO_DW2_OFFSET 0x05C
| RX FIFO Data Word 2. More...
#define | XCAN_AFR_OFFSET 0x060
| Acceptance Filter Register. More...
#define | XCAN_AFMR1_OFFSET 0x064
| Acceptance Filter Mask Register 1. More...
#define | XCAN_AFIR1_OFFSET 0x068
| Acceptance Filter ID Register 1. More...
#define | XCAN_AFMR2_OFFSET 0x06C
| Acceptance Filter Mask Register 2. More...
#define | XCAN_AFIR2_OFFSET 0x070
| Acceptance Filter ID Register 2. More...
#define | XCAN_AFMR3_OFFSET 0x074
| Acceptance Filter Mask Register 3. More...
#define | XCAN_AFIR3_OFFSET 0x078
| Acceptance Filter ID Register 3. More...
#define | XCAN_AFMR4_OFFSET 0x07C
| Acceptance Filter Mask Register 4. More...
#define | XCAN_AFIR4_OFFSET 0x080
| Acceptance Filter ID Register 4. More...
#define | XCAN_ECC_CFG_OFFSET 0x0C8
| ECC Configuration register. More...
#define | XCAN_TXTLFIFO_ECC_OFFSET 0x0CC
| TXTL FIFO ECC error counter. More...
#define | XCAN_TXOLFIFO_ECC_OFFSET 0x0D0
| TXOL FIFO ECC error counter. More...
#define | XCAN_RXFIFO_ECC_OFFSET 0X0D4
| RX FIFO ECC error counter. More...
Software Reset Register
#define | XCAN_SRR_CEN_MASK 0x00000002
| Can Enable Mask. More...
#define | XCAN_SRR_SRST_MASK 0x00000001
| Reset Mask. More...
Mode Select Register
#define | XCAN_MSR_LBACK_MASK 0x00000002
| Loop Back Mode Select Mask. More...
#define | XCAN_MSR_SLEEP_MASK 0x00000001
| Sleep Mode Select Mask. More...
Baud Rate Prescaler register
#define | XCAN_BRPR_BRP_MASK 0x000000FF
| Baud Rate Prescaler Mask. More...
Bit Timing Register
#define | XCAN_BTR_SJW_MASK 0x00000180
| Sync Jump Width Mask. More...
#define | XCAN_BTR_SJW_SHIFT 7
| Sync Jump Width Shift. More...
#define | XCAN_BTR_TS2_MASK 0x00000070
| Time Segment 2 Mask. More...
#define | XCAN_BTR_TS2_SHIFT 4
| Time Segment 2 Shift. More...
#define | XCAN_BTR_TS1_MASK 0x0000000F
| Time Segment 1 Mask. More...
Error Counter Register
#define | XCAN_ECR_REC_MASK 0x0000FF00
| Receive Error Counter Mask. More...
#define | XCAN_ECR_REC_SHIFT 8
| Receive Error Counter Shift. More...
#define | XCAN_ECR_TEC_MASK 0x000000FF
| Transmit Error Counter Mask. More...
Error Status Register
#define | XCAN_ESR_ACKER_MASK 0x00000010
| ACK Error Mask. More...
#define | XCAN_ESR_BERR_MASK 0x00000008
| Bit Error Mask. More...
#define | XCAN_ESR_STER_MASK 0x00000004
| Stuff Error Mask. More...
#define | XCAN_ESR_FMER_MASK 0x00000002
| Form Error Mask. More...
#define | XCAN_ESR_CRCER_MASK 0x00000001
| CRC Error Mask. More...
Status Register
#define | XCAN_SR_ACFBSY_MASK 0x00000800
| Acceptance Filter busy Mask. More...
#define | XCAN_SR_TXFLL_MASK 0x00000400
| TX FIFO is full Mask. More...
#define | XCAN_SR_TXBFLL_MASK 0x00000200
| TX High Priority Buffer full. More...
#define | XCAN_SR_ESTAT_MASK 0x00000180
| Error Status Mask. More...
#define | XCAN_SR_ESTAT_SHIFT 7
| Error Status Shift. More...
#define | XCAN_SR_ERRWRN_MASK 0x00000040
| Error Warning Mask. More...
#define | XCAN_SR_BBSY_MASK 0x00000020
| Bus Busy Mask. More...
#define | XCAN_SR_BIDLE_MASK 0x00000010
| Bus Idle Mask. More...
#define | XCAN_SR_NORMAL_MASK 0x00000008
| Normal Mode Mask. More...
#define | XCAN_SR_SLEEP_MASK 0x00000004
| Sleep Mode Mask. More...
#define | XCAN_SR_LBACK_MASK 0x00000002
| Loop Back Mode Mask. More...
#define | XCAN_SR_CONFIG_MASK 0x00000001
| Configuration Mode Mask. More...
Interrupt Status/Enable/Clear Register
#define | XCAN_IXR_E2BERX_MASK 0x00800000
| RX FIFO two bit ECC error. More...
#define | XCAN_IXR_E1BERX_MASK 0x00400000
| RX FIFO one bit ECC error. More...
#define | XCAN_IXR_E2BETXOL_MASK 0x00200000
| TXOL FIFO two bit ECC error. More...
#define | XCAN_IXR_E1BETXOL_MASK 0x00100000
| TXOL FIFO one bit ECC error. More...
#define | XCAN_IXR_E2BETXTL_MASK 0x00080000
| TXTL FIFO two bit ECC error. More...
#define | XCAN_IXR_E1BETXTL_MASK 0x00040000
| TXTL FIFO one bit ECC error. More...
#define | XCAN_IXR_WKUP_MASK 0x00000800
| Wake up Interrupt Mask. More...
#define | XCAN_IXR_SLP_MASK 0x00000400
| Sleep Interrupt Mask. More...
#define | XCAN_IXR_BSOFF_MASK 0x00000200
| Bus Off Interrupt Mask. More...
#define | XCAN_IXR_ERROR_MASK 0x00000100
| Error Interrupt Mask. More...
#define | XCAN_IXR_RXNEMP_MASK 0x00000080
| RX FIFO Not Empty Intr Mask. More...
#define | XCAN_IXR_RXOFLW_MASK 0x00000040
| RX FIFO Overflow Intr Mask. More...
#define | XCAN_IXR_RXUFLW_MASK 0x00000020
| RX FIFO Underflow Intr Mask. More...
#define | XCAN_IXR_RXOK_MASK 0x00000010
| New Message Received Intr. More...
#define | XCAN_IXR_TXBFLL_MASK 0x00000008
| TX High Priority Buf Full. More...
#define | XCAN_IXR_TXFLL_MASK 0x00000004
| TX FIFO Full Interrupt Mask. More...
#define | XCAN_IXR_TXOK_MASK 0x00000002
| TX Successful Interrupt Mask. More...
#define | XCAN_IXR_ARBLST_MASK 0x00000001
| Arbitration Lost Intr Mask. More...
#define | XCAN_IXR_ECC_MASK
| Mask for ECC interrupts. More...
#define | XCAN_IXR_ALL
| Mask for basic interrupts. More...
CAN Frame Identifier (TX High Priority Buffer/TX/RX/Acceptance Filter
Mask/Acceptance Filter ID)
#define | XCAN_IDR_ID1_MASK 0xFFE00000
| Standard Messg Ident Mask. More...
#define | XCAN_IDR_ID1_SHIFT 21
| Standard Messg Ident Shift. More...
#define | XCAN_IDR_SRR_MASK 0x00100000
| Substitute Remote TX Req. More...
#define | XCAN_IDR_SRR_SHIFT 20
| Shift Value for SRR. More...
#define | XCAN_IDR_IDE_MASK 0x00080000
| Identifier Extension Mask. More...
#define | XCAN_IDR_IDE_SHIFT 19
| Identifier Extension Shift. More...
#define | XCAN_IDR_ID2_MASK 0x0007FFFE
| Extended Message Ident Mask. More...
#define | XCAN_IDR_ID2_SHIFT 1
| Extended Message Ident Shift. More...
#define | XCAN_IDR_RTR_MASK 0x00000001
| Remote TX Request Mask. More...
CAN Frame Data Length Code (TX High Priority Buffer/TX/RX)
#define | XCAN_DLCR_DLC_MASK 0xF0000000
| Data Length Code Mask. More...
#define | XCAN_DLCR_DLC_SHIFT 28
| Data Length Code Shift. More...
CAN Frame Data Word 1 (TX High Priority Buffer/TX/RX)
#define | XCAN_DW1R_DB0_MASK 0xFF000000
| Data Byte 0 Mask. More...
#define | XCAN_DW1R_DB0_SHIFT 24
| Data Byte 0 Shift. More...
#define | XCAN_DW1R_DB1_MASK 0x00FF0000
| Data Byte 1 Mask. More...
#define | XCAN_DW1R_DB1_SHIFT 16
| Data Byte 1 Shift. More...
#define | XCAN_DW1R_DB2_MASK 0x0000FF00
| Data Byte 2 Mask. More...
#define | XCAN_DW1R_DB2_SHIFT 8
| Data Byte 2 Shift. More...
#define | XCAN_DW1R_DB3_MASK 0x000000FF
| Data Byte 3 Mask. More...
CAN Frame Data Word 2 (TX High Priority Buffer/TX/RX)
#define | XCAN_DW2R_DB4_MASK 0xFF000000
| Data Byte 4 Mask. More...
#define | XCAN_DW2R_DB4_SHIFT 24
| Data Byte 4 Shift. More...
#define | XCAN_DW2R_DB5_MASK 0x00FF0000
| Data Byte 5 Mask. More...
#define | XCAN_DW2R_DB5_SHIFT 16
| Data Byte 5 Shift. More...
#define | XCAN_DW2R_DB6_MASK 0x0000FF00
| Data Byte 6 Mask. More...
#define | XCAN_DW2R_DB6_SHIFT 8
| Data Byte 6 Shift. More...
#define | XCAN_DW2R_DB7_MASK 0x000000FF
| Data Byte 7. More...
Acceptance Filter Register
#define | XCAN_AFR_UAF4_MASK 0x00000008
| Use Acceptance Filter No.4. More...
#define | XCAN_AFR_UAF3_MASK 0x00000004
| Use Acceptance Filter No.3. More...
#define | XCAN_AFR_UAF2_MASK 0x00000002
| Use Acceptance Filter No.2. More...
#define | XCAN_AFR_UAF1_MASK 0x00000001
| Use Acceptance Filter No.1. More...
#define | XCAN_AFR_UAF_ALL_MASK
| Mask for Acceptance Filters. More...
ECC Configuration register
#define | XCAN_ECC_CFG_RST_MASK 0x00000007
| Reset Mask for ECC configuration register. More...
#define | XCAN_ECC_CFG_REECRX_MASK 0x00000004
| Reset RX FIFO ECC error counters. More...
#define | XCAN_ECC_CFG_REECTXOL_MASK 0x00000002
| Reset TXOL FIFO ECC error counters. More...
#define | XCAN_ECC_CFG_REECTXTL_MASK 0x00000001
| Reset TXTL FIFO ECC error counters. More...
#define | XCAN_ECC_2BIT_SHIFT 16
| ECC 2bit error counter shift. More...
CAN frame length constants
#define | XCAN_MAX_FRAME_SIZE 16
| Maximum CAN frame length in bytes. More...
Mask for Low 16bits and High 16 bits
#define | XCAN_MASK_LOW_16BITS 0x0000FFFF
| Mask to obtain lower 16bits. More...
#define | XCAN_MASK_HIGH_16BITS 0XFFFF0000
| Mask to obtain higher 16bits. More...