| i3c Vitis Drivers API Documentation

- Overview
- Data Structures
- APIs
- File List
- Examples

Data Structures | Macros | Typedefs | Functions | Variables
Overview

## Data Structures
struct | XI3c_Config
| This typedef contains configuration information for the device. More...
struct | XI3c_SlaveInfo
| The XI3c slave data. More...
struct | XI3c
| The XI3c driver instance data. More...

## Macros
#define | XI3C_H
| by using protection macros More...
#define | TIMEOUT_COUNTER 2000000U
| Wait for 2 sec in worst case. More...
#define | XI3c_BusIsBusy(BaseAddress) (XI3c_ReadReg((BaseAddress), XI3C_SR_OFFSET) & XI3C_SR_BUS_BUSY_MASK)
| Checks whether the I3C bus is busy. More...
#define | XI3c_GetDynaAddr(InstancePtr)
| Gets the dynamic address of the I3C. More...
#define | XI3c_SetSclHighTime(InstancePtr, Val)
| Sets scl high time of I3C. More...
#define | XI3c_GetSclHighTime(InstancePtr)
| Gets scl high time of I3C. More...
#define | XI3c_SetSclLowTime(InstancePtr, Val)
| Sets scl low time of I3C. More...
#define | XI3c_GetSclLowTime(InstancePtr)
| Gets scl low time of I3C. More...
#define | XI3c_SetSdaHoldTime(InstancePtr, Val)
| Sets sda hold time of I3C. More...
#define | XI3c_GetSdaHoldTime(InstancePtr)
| Gets sda hold time of I3C. More...
#define | XI3c_SetBusIdleTime(InstancePtr, Val)
| Sets bus idle time of I3C. More...
#define | XI3c_GetBusIdleTime(InstancePtr)
| Gets bus idle time of I3C. More...
#define | XI3c_SetTsuStartTime(InstancePtr, Val)
| Sets Tsu Start time of I3C. More...
#define | XI3c_GetTsuStartTime(InstancePtr)
| Gets Tsu Start time of I3C. More...
#define | XI3c_SetThdStartTime(InstancePtr, Val)
| Sets Thd Start time of I3C. More...
#define | XI3c_GetThdStartTime(InstancePtr)
| This function gets Thd Start time. More...
#define | XI3c_SetTsuStopTime(InstancePtr, Val)
| Sets Tsu Stop time of I3C. More...
#define | XI3c_GetTsuStopTime(InstancePtr)
| Gets Tsu Stop time of I3C. More...
#define | XI3c_SetSclOdHighTime(InstancePtr, Val)
| Sets Scl open drain high time of I3C. More...
#define | XI3c_GetSclOdHighTime(InstancePtr)
| Gets Scl open drain high time of I3C. More...
#define | XI3c_SetSclOdLowTime(InstancePtr, Val)
| Sets Scl open drain low time of I3C. More...
#define | XI3c_GetSclOdLowTime(InstancePtr)
| Gets Scl open drain low time of I3C. More...
#define | XI3c_GetRevisionNumber(InstancePtr)
| Gets Core Revision number of I3C. More...
#define | XI3c_GetResponseData(InstancePtr)
| Gets Response data of I3C. More...
#define | XI3c_GetErrorStatus(InstancePtr)
| Gets error status from response of I3C. More...
#define | XI3c_IsDyncAddrAssigned(InstancePtr)
| Check the dynamic address assignment status of I3C in slave mode. More...
#define | XI3c_IsRespAvailable(InstancePtr)
| Check the response status of I3C. More...
#define | XI3c_SetDeviceStatus(InstancePtr, Format1, Format2)
| Sets device status of I3C. More...
#define | XI3c_SetMaxDataSpeed(InstancePtr, Format1, Format3)
| Sets device Max data speed. More...
#define | XI3c_SetCapsFormat1(InstancePtr, Cap1, Cap2, Cap3, Cap4)
| Sets device capabilities format1. More...
#define | XI3c_SetCapsFormat2(InstancePtr, Cap1, Cap2)
| Sets device capabilities format2. More...
#define | XI3C_HW_H_
| < prevent circular inclusions More...
#define | XI3C_BASEADDR 0x0
| AXI_I3C0 Base Address #define XI3C_BASEADDR 0x80000000. More...

## Typedefs
typedef void(* | XI3c_IntrHandler )(u32 StatusEvent)
| The handler data type allows the user to define a callback function to respond to interrupt events in the system. More...

## Functions
void | XI3c_ConfigIbi (XI3c *InstancePtr, u8 DevCount)
| This configure target address and BCR register values of available devices to the controller RAM. More...
void | XI3C_BusInit (XI3c *InstancePtr)
| Initializes the XI3c slaves devices by disable/enable events and reset dynamic addresses. More...
s32 | XI3c_CfgInitialize (XI3c *InstancePtr, XI3c_Config *ConfigPtr, u32 EffectiveAddr)
| Initializes a specific XI3c instance such that the driver is ready to use. More...
void | XI3c_FillCmdFifo (XI3c *InstancePtr, XI3c_Cmd *Cmd)
| Fill I3C Command fifo. More...
void | XI3c_WriteTxFifo (XI3c *InstancePtr)
| Fill I3C Write Tx FIFO. More...
void | XI3c_ReadRxFifo (XI3c *InstancePtr)
| Read RX I3C FIFO. More...
s32 | XI3c_DynaAddrAssign (XI3c *InstancePtr, u8 DynaAddr[], u8 DevCount)
| This function sends dynamic Address Assignment for available devices. More...
XI3c_Config * | XI3c_LookupConfig (u16 DeviceId)
| Looks up the device configuration based on the unique device ID. More...
s32 | XI3c_SendTransferCmd (XI3c *InstancePtr, XI3c_Cmd *Cmd, u8 Data)
| This function sends the command. More...
s32 | XI3c_SetSClk (XI3c *InstancePtr, u32 SclkHz, u8 Mode)
| Sets I3C Scl clock frequency. More...
void | XI3c_SetStatusHandler (XI3c *InstancePtr, XI3c_IntrHandler FunctionPtr)
| This function sets the status handler, which the driver calls when it encounters conditions that should be reported to the higher layer software. More...
s32 | XI3c_MasterSend (XI3c *InstancePtr, XI3c_Cmd *Cmd, u8 *MsgPtr, u16 ByteCount)
| This function initiates a interrupt mode send in master mode. More...
s32 | XI3c_MasterRecv (XI3c *InstancePtr, XI3c_Cmd *Cmd, u8 *MsgPtr, u16 ByteCount)
| This function initiates a interrupt mode receive in master mode. More...
s32 | XI3c_MasterSendPolled (XI3c *InstancePtr, XI3c_Cmd *Cmd, u8 *MsgPtr, u16 ByteCount)
| This function initiates a polled mode send in master mode. More...
s32 | XI3c_MasterRecvPolled (XI3c *InstancePtr, XI3c_Cmd *Cmd, u8 *MsgPtr, u16 ByteCount)
| This function initiates a polled mode receive in master mode. More...
void | XI3c_MasterInterruptHandler (XI3c *InstancePtr)
| The interrupt handler for the master mode. More...
s32 | XI3c_IbiRecv (XI3c *InstancePtr, u8 *MsgPtr)
| This function setup for receive during IBI in interrupt mode. More...
s32 | XI3c_IbiRecvPolled (XI3c *InstancePtr, u8 *MsgPtr)
| This function receives data during IBI in polled mode. More...
s32 | XI3c_SlaveSend (XI3c *InstancePtr, u8 *MsgPtr, u16 ByteCount)
| This function initiates a interrupt mode send in slave mode. More...
s32 | XI3c_SlaveRecv (XI3c *InstancePtr, u8 *MsgPtr)
| This function initiates a interrupt mode receive in slave mode. More...
s32 | XI3c_SlaveSendPolled (XI3c *InstancePtr, u8 *MsgPtr, u16 ByteCount)
| This function initiates a polled mode send in slave mode. More...
s32 | XI3c_SlaveRecvPolled (XI3c *InstancePtr, u8 *MsgPtr)
| This function initiates a polled mode receive in slave mode. More...
void | XI3c_SlaveInterruptHandler (XI3c *InstancePtr)
| The interrupt handler for the slave mode. More...

## Variables
XI3c_Config | XI3c_ConfigTable []
| Configuration table. More...
XI3c_Config | XI3c_ConfigTable [XPAR_XI3C_NUM_INSTANCES]
| This table contains configuration information for each I3C device in the system. More...
#define | XI3C_VERSION_OFFSET 0x00
| Register offsets for the XI3c device. More...
#define | XI3C_RESET_OFFSET 0x04
| Soft Reset Register. More...
#define | XI3C_CR_OFFSET 0x08
| Control Register. More...
#define | XI3C_ADDRESS_OFFSET 0x0C
| Target Address Register. More...
#define | XI3C_SR_OFFSET 0x10
| Status Register. More...
#define | XI3C_INTR_STATUS_OFFSET 0x14
| Status Event Register. More...
#define | XI3C_INTR_RE_OFFSET 0x18
| Status Event Enable(Rising Edge) Register. More...
#define | XI3C_INTR_FE_OFFSET 0x1C
| Status Event Enable(Falling Edge) Register. More...
#define | XI3C_CMD_FIFO_OFFSET 0x20
| I3C Command FIFO Register. More...
#define | XI3C_WR_FIFO_OFFSET 0x24
| I3C Write Data FIFO Register. More...
#define | XI3C_RD_FIFO_OFFSET 0x28
| I3C Read Data FIFO Register. More...
#define | XI3C_RESP_STATUS_FIFO_OFFSET 0x2C
| I3C Response status FIFO Register. More...
#define | XI3C_FIFO_LVL_STATUS_OFFSET 0x30
| I3C CMD & WR FIFO LVL Register. More...
#define | XI3C_FIFO_LVL_STATUS_1_OFFSET 0x34
| I3C RESP & RD FIFO LVL Register. More...
#define | XI3C_SCL_HIGH_TIME_OFFSET 0x38
| I3C SCL HIGH Register. More...
#define | XI3C_SCL_LOW_TIME_OFFSET 0x3C
| I3C SCL LOW Register. More...
#define | XI3C_SDA_HOLD_TIME_OFFSET 0x40
| I3C SDA HOLD Register. More...
#define | XI3C_BUS_IDLE_OFFSET 0x44
| I3C CONTROLLER BUS IDLE Register. More...
#define | XI3C_TSU_START_OFFSET 0x48
| I3C START SETUP Register. More...
#define | XI3C_THD_START_OFFSET 0x4C
| I3C START HOLD Register. More...
#define | XI3C_TSU_STOP_OFFSET 0x50
| I3C STOP Setup Register. More...
#define | XI3C_OD_SCL_HIGH_TIME_OFFSET 0x54
| I3C OD SCL HIGH Register. More...
#define | XI3C_OD_SCL_LOW_TIME_OFFSET 0x58
| I3C OD SCL LOW Register. More...
#define | XI3C_TARGET_ADDR_BCR 0x60
| I3C Target dynamic Address and BCR Register. More...
#define | XI3C_MWL_MRL 0x74
| Maximum Write and Max Read length. More...
#define | XI3C_EVENT 0x78
| Target events. More...
#define | XI3C_GETMXDS 0x80
| Target Device Max Data Speed. More...
#define | XI3C_GETSTATUS 0x84
| Target Device current Status. More...
#define | XI3C_GETCAPS_REG0 0x88
| Target Device Format 1 Capabilities. More...
#define | XI3C_GETCAPS_REG1 0x8c
| Target Device Format 2 Capabilities. More...
#define | XI3C_CON_RD_BYTE_COUNT 0x90
| Read byte count register. More...

## Version Register mask(s)
#define | XI3C_INTERNAL_REVISION_MASK 0x0000000F
| BITS 3:0 - Internal revision. More...
#define | XI3C_CORE_PATCH_REVISION_MASK 0x000000F0
| BITS 7:4 - Patch revision. More...
#define | XI3C_CORE_REVISION_NUM_MASK 0x0000FF00
| BITS 15:8 - Revision number. More...
#define | XI3C_CORE_VERSION_MINOR_MASK 0x00FF0000
| BITS 23:16 - Minor version. More...
#define | XI3C_CORE_VERSION_MAJOR_MASK 0xFF000000
| BITS 31:24 - Major version. More...
#define | XI3C_CORE_REVISION_NUM_SHIFT 8
| Revision number shift. More...

## Reset Register mask(s)
#define | XI3C_SOFT_RESET_MASK 0x00000001
| BIT 0 - Reset. More...
#define | XI3C_CMD_FIFO_RESET_MASK 0x00000002
| BIT 1 - Cmd fifo reset. More...
#define | XI3C_WR_FIFO_RESET_MASK 0x00000004
| BIT 2 - Write fifo reset. More...
#define | XI3C_RD_FIFO_RESET_MASK 0x00000008
| BIT 3 - Read fifo reset. More...
#define | XI3C_RESP_FIFO_RESET_MASK 0x00000010
| BIT 4 - Response fifo reset. More...
#define | XI3C_ALL_FIFOS_RESET_MASK 0x0000001E
| BIT 1 to 4 - All fifos reset. More...

## Control Register (CR) mask(s)
#define | XI3C_CR_EN_MASK 0x00000001
| BIT 0 - Core Enable. More...
#define | XI3C_CR_ABORT_MASK 0x00000002
| BIT 1 - Abort Transaction. More...
#define | XI3C_CR_RESUME_MASK 0x00000004
| BIT 2 - Resume Operation. More...
#define | XI3C_CR_IBI_MASK 0x00000008
| BIT 3 - IBI Enable. More...
#define | XI3C_CR_HJ_MASK 0x00000010
| BIT 4 - Hot Join Enable. More...
#define | XI3C_CR_ACCEPT_CTRL_ROLE_REQ 0x00000020
| BIT 5 - Generate ACK for secondary controller role request IBI. More...

## Status Register (SR) mask(s)
#define | XI3C_SR_BUS_BUSY_MASK 0x00000001
| BIT 0 - Bus Busy. More...
#define | XI3C_SR_CLK_STALL_MASK 0x00000002
| BIT 1 - Clock Stall. More...
#define | XI3C_SR_CMD_FULL_MASK 0x00000004
| BIT 2 - Cmd Fifo Full. More...
#define | XI3C_SR_RESP_FULL_MASK 0x00000008
| BIT 3 - Resp Fifo Full. More...
#define | XI3C_SR_RESP_NOT_EMPTY_MASK 0x00000010
| BIT 4 - Resp Fifo not empty. More...
#define | XI3C_SR_WR_FULL_MASK 0x00000020
| BIT 5 - Write Fifo Full. More...
#define | XI3C_SR_RD_FULL_MASK 0x00000040
| BIT 6 - Read Fifo Full. More...
#define | XI3C_SR_IBI_MASK 0x00000080
| BIT 7 - IBI. More...
#define | XI3C_SR_HJ_MASK 0x00000100
| BIT 8 - Hot join. More...
#define | XI3C_SR_CTRL_ROLE_REQUEST_MASK 0x00000200
| BIT 9 - Received control role request. More...
#define | XI3C_SR_ERROR_TYPE_CE3_MASK 0x00000400
| BIT 10 - This field will be set if there is no START coming from the new Controller that has took over the Role. More...
#define | XI3C_SR_RETURN_ROLE_REQ_ACK_MASK 0x00000800
| BIT 11 - Received ACK on controller role request back. More...
#define | XI3C_SR_RD_FIFO_ALMOST_FULL_MASK 0x00001000
| BIT 12 - Read Fifo almost Full. More...
#define | XI3C_SR_CMD_FIFO_NOT_EMPTY_MASK 0x00002000
| BIT 13 - CMD FIFO empty. More...
#define | XI3C_SR_WR_FIFO_NOT_EMPTY_MASK 0x00004000
| BIT 14 - Write FIFO empty. More...
#define | XI3C_SR_RD_FIFO_NOT_EMPTY_MASK 0x00008000
| BIT 15 - Read FIFO empty. More...
#define | XI3C_SR_SLV_DYNC_ADDR_DONE_MASK 0x00080000
| BIT 19 - Dynamic address assigned to slave. More...

## Status Register (SR) Shifts(s)
#define | XI3C_SR_BUS_BUSY_SHIFT 0
| BIT 0 - Bus Busy. More...
#define | XI3C_SR_CLK_STALL_SHIFT 1
| BIT 1 - Clock Stall. More...
#define | XI3C_SR_CMD_FULL_SHIFT 2
| BIT 2 - Cmd Fifo Full. More...
#define | XI3C_SR_RESP_FULL_SHIFT 3
| BIT 3 - Resp Fifo Full. More...
#define | XI3C_SR_RESP_NOT_EMPTY_SHIFT 4
| BIT 4 - Resp Fifo not empty. More...
#define | XI3C_SR_WR_FULL_SHIFT 5
| BIT 5 - Write Fifo Full. More...
#define | XI3C_SR_RD_FULL_SHIFT 6
| BIT 6 - Read Fifo Full. More...
#define | XI3C_SR_SLV_DYNC_ADDR_DONE_SHIFT 19
| BIT 19 - Dynamic address assigned to slave. More...

## response and other mask(s)
#define | XI3C_RESP_ID_MASK 0x0000000F
#define | XI3C_RESP_RW_MASK 0x00000010
#define | XI3C_RESP_CODE_MASK 0x000001E0
#define | XI3C_RESP_BYTES_MASK 0x001FFE00
#define | XI3C_SLV_RESP_CCC_MASK 0x1FE00000
#define | XI3C_SLV_RESP_7E_FRAME_MASK 0x20000000
#define | XI3C_MRL_MASK 0x0FFF0000
#define | XI3C_GRP_ADDR_MASK 0x0000FF00

## response and other shift(s)
#define | XI3C_RESP_TID_SHIFT 0
#define | XI3C_RESP_RW_SHIFT 4
#define | XI3C_RESP_CODE_SHIFT 5
#define | XI3C_RESP_BYTES_SHIFT 9
#define | XI3C_RESP_LVL_SHIFT 16
#define | XI3C_SLV_RESP_CCC_SHIFT 21
#define | XI3C_SLV_RESP_7E_FRAME_SHIFT 29
#define | XI3C_CMD_LVL_SHIFT 16
#define | XI3C_MRL_SHIFT 16
#define | XI3C_MWL_MRL_MSB_SHIFT 8
#define | XI3C_GRP_ADDR_SHIFT 8
#define | XI3C_GETSTATUS_FORMAT2_SHIFT 16
#define | XI3C_GETMXDS_FORMAT3_DATA_SHIFT 16
#define | XI3C_CAPS4_SHIFT 24
#define | XI3C_CAPS3_SHIFT 16
#define | XI3C_CAPS2_SHIFT 8

## bit masks
#define | XI3C_1BIT_MASK 0x00000001
#define | XI3C_2BITS_MASK 0x00000003
#define | XI3C_3BITS_MASK 0x00000007
#define | XI3C_4BITS_MASK 0x0000000F
#define | XI3C_5BITS_MASK 0x0000001F
#define | XI3C_6BITS_MASK 0x0000003F
#define | XI3C_7BITS_MASK 0x0000007F
#define | XI3C_8BITS_MASK 0x000000FF
#define | XI3C_9BITS_MASK 0x000001FF
#define | XI3C_10BITS_MASK 0x000003FF
#define | XI3C_11BITS_MASK 0x000007FF
#define | XI3C_12BITS_MASK 0x00000FFF
#define | XI3C_13BITS_MASK 0x00001FFF
#define | XI3C_14BITS_MASK 0x00003FFF
#define | XI3C_15BITS_MASK 0x00007FFF
#define | XI3C_16BITS_MASK 0x0000FFFF
#define | XI3C_17BITS_MASK 0x0001FFFF
#define | XI3C_18BITS_MASK 0x0003FFFF
#define | XI3C_19BITS_MASK 0x0007FFFF
#define | XI3C_20BITS_MASK 0x000FFFFF
#define | XI3C_MSB_8BITS_MASK 0x0000FF00
#define | XI3C_MSB_16BITS_MASK 0xFFFF0000

## interrupt Register (INTR) mask(s)
#define | XI3C_INTR_BUS_BUSY_MASK 0x00000001
| BIT 0 - Bus Busy. More...
#define | XI3C_INTR_CLK_STALL_MASK 0x00000002
| BIT 1 - Clock Stall. More...
#define | XI3C_INTR_CMD_FULL_MASK 0x00000004
| BIT 2 - Cmd Fifo Full. More...
#define | XI3C_INTR_RESP_FULL_MASK 0x00000008
| BIT 3 - Resp Fifo Full. More...
#define | XI3C_INTR_RESP_NOT_EMPTY_MASK 0x00000010
| BIT 4 - Resp Fifo not empty. More...
#define | XI3C_INTR_WR_FIFO_ALMOST_FULL_MASK 0x00000020
| BIT 5 - Write Fifo Full. More...
#define | XI3C_INTR_RD_FULL_MASK 0x00000040
| BIT 6 - Read Fifo Full. More...
#define | XI3C_ALL_INTR_MASK 0x0000007F
| 6:0 BITS More...
#define | XI3C_INTR_IBI_MASK 0x00000080
| BIT 7 - IBI. More...
#define | XI3C_INTR_HJ_MASK 0x00000100
| BIT 8 - Hot join. More...
#define | XI3C_INTR_CTRL_ROLE_REQUEST_MASK 0x00000200
| BIT 9 - Received control role request. More...
#define | XI3C_INTR_ERROR_TYPE_CE3_MASK 0x00000400
| BIT 10 - This field will be set if there is no START coming from the new Controller that has took over the Role. More...
#define | XI3C_INTR_RETURN_ROLE_REQ_ACK_MASK 0x00000800
| BIT 11 - Received ACK on controller role request back. More...
#define | XI3C_INTR_RD_FIFO_ALMOST_FULL_MASK 0x00001000
| BIT 12 - Read Fifo almost Full. More...
#define | XI3C_INTR_CMD_FIFO_NOT_EMPTY_MASK 0x00002000
| BIT 13 - CMD FIFO empty. More...
#define | XI3C_INTR_WR_FIFO_NOT_EMPTY_MASK 0x00004000
| BIT 14 - Write FIFO empty. More...
#define | XI3C_INTR_RD_FIFO_NOT_EMPTY_MASK 0x00008000
| BIT 15 - Read FIFO empty. More...
#define | XI3c_ReadReg(BaseAddress, RegOffset) XI3c_In32((BaseAddress) + (u32)(RegOffset))
| Read an I3C register. More...
#define | XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue) XI3c_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
| Write an I3C register. More...
#define | XI3c_WrFifoLevel(InstancePtr)
| Read WR FIFO LEVEL. More...
#define | XI3c_CmdFifoLevel(InstancePtr)
| Read CMD FIFO LEVEL. More...
#define | XI3c_RdFifoLevel(InstancePtr)
| Read RD FIFO LEVEL. More...
#define | XI3c_RespFifoLevel(InstancePtr)
| Read RESP FIFO LEVEL. More...
#define | XI3c_RxFifoNotEmpty(InstancePtr)
| Check Read FIFO empty status. More...
#define | XI3c_RespFifoNotEmpty(InstancePtr)
| Check Response FIFO empty status. More...
#define | XI3c_EnableREInterrupts(BaseAddress, IntrMask)
| Enable Raising edge interrupts. More...
#define | XI3c_EnableFEInterrupts(BaseAddress, IntrMask)
| Enable Faling edge interrupts. More...
#define | XI3c_DisableREInterrupts(BaseAddress, IntrMask)
| Disable raising edge interrupts. More...
#define | XI3c_DisableFEInterrupts(BaseAddress, IntrMask)
| Disable faling edge interrupts. More...
#define | XI3c_DisableAllREInterrupts(BaseAddress)
| Disable all raising edge interrupts. More...
#define | XI3c_DisableAllFEInterrupts(BaseAddress)
| Disable all faling edge interrupts. More...
#define | XI3c_FillSlaveSendCount(InstancePtr, ByteCount)
| Fill Slave send byte count value. More...
#define | XI3c_ClearGrpAddr(InstancePtr)
| Clear the group address of target. More...
#define | XI3c_GetMWL(InstancePtr)
| Read Maximum write length. More...
#define | XI3c_GetMRL(InstancePtr)
| Read Maximum read length. More...

## Macro Definition Documentation

#define TIMEOUT_COUNTER 2000000U

Wait for 2 sec in worst case.

Referenced by XI3c_IbiRecvPolled().

#define XI3C_ADDRESS_OFFSET 0x0C

Target Address Register.

#define XI3C_ALL_FIFOS_RESET_MASK 0x0000001E

BIT 1 to 4 - All fifos reset.

#define XI3C_ALL_INTR_MASK 0x0000007F

6:0 BITS

#define XI3C_BASEADDR 0x0

AXI_I3C0 Base Address #define XI3C_BASEADDR 0x80000000.

#define XI3C_BUS_IDLE_OFFSET 0x44

I3C CONTROLLER BUS IDLE Register.

#define XI3c_BusIsBusy | ( |  | BaseAddress | ) | (XI3c_ReadReg((BaseAddress), XI3C_SR_OFFSET) & XI3C_SR_BUS_BUSY_MASK)

Checks whether the I3C bus is busy.

Parameters

  InstancePtr | is a pointer to the XI3c instance.

Returns
  None.

Note
  C-style signature: s32 XI3c_BusIsBusy(XI3c *InstancePtr)

#define XI3c_ClearGrpAddr | ( |  | InstancePtr | ) |

Value:
XI3c_WriteReg((InstancePtr->Config.BaseAddress), \
XI3C_ADDRESS_OFFSET, \
((XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_ADDRESS_OFFSET)) \
& (~XI3C_GRP_ADDR_MASK)))
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c_WriteReg
#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an I3C register.
Definition: xi3c_hw.h:292
XI3C_ADDRESS_OFFSET
#define XI3C_ADDRESS_OFFSET
Target Address Register.
Definition: xi3c_hw.h:60
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778

Clear the group address of target.

Parameters

  InstancePtr | is a pointer to the XI3c core instance.
  Byte | count value.

Returns
  None.

Note
  C-style signature: void XI3c_FillSlaveSendCount(XI3c *InstancePtr, u16 ByteCount)

#define XI3C_CMD_FIFO_OFFSET 0x20

I3C Command FIFO Register.

Referenced by XI3c_FillCmdFifo().

#define XI3C_CMD_FIFO_RESET_MASK 0x00000002

BIT 1 - Cmd fifo reset.

#define XI3c_CmdFifoLevel | ( |  | InstancePtr | ) |

Value:
(u16)((XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_FIFO_LVL_STATUS_OFFSET) & \
XI3C_MSB_16BITS_MASK) >> XI3C_CMD_LVL_SHIFT)
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778
XI3C_FIFO_LVL_STATUS_OFFSET
#define XI3C_FIFO_LVL_STATUS_OFFSET
I3C CMD &amp; WR FIFO LVL Register.
Definition: xi3c_hw.h:69

Read CMD FIFO LEVEL.

Parameters

  InstancePtr | is a pointer to the XI3c core instance.

Returns
  None.

Note
  C-style signature: u16 XI3c_CmdFifoLevel(XI3c *InstancePtr)

#define XI3C_CON_RD_BYTE_COUNT 0x90

Read byte count register.

#define XI3C_CORE_PATCH_REVISION_MASK 0x000000F0

BITS 7:4 - Patch revision.

#define XI3C_CORE_REVISION_NUM_MASK 0x0000FF00

BITS 15:8 - Revision number.

#define XI3C_CORE_REVISION_NUM_SHIFT 8

Revision number shift.

#define XI3C_CORE_VERSION_MAJOR_MASK 0xFF000000

BITS 31:24 - Major version.

#define XI3C_CORE_VERSION_MINOR_MASK 0x00FF0000

BITS 23:16 - Minor version.

#define XI3C_CR_ABORT_MASK 0x00000002

BIT 1 - Abort Transaction.

#define XI3C_CR_ACCEPT_CTRL_ROLE_REQ 0x00000020

BIT 5 - Generate ACK for secondary controller role request IBI.

#define XI3C_CR_EN_MASK 0x00000001

BIT 0 - Core Enable.

#define XI3C_CR_HJ_MASK 0x00000010

BIT 4 - Hot Join Enable.

#define XI3C_CR_IBI_MASK 0x00000008

BIT 3 - IBI Enable.

#define XI3C_CR_OFFSET 0x08

Control Register.

#define XI3C_CR_RESUME_MASK 0x00000004

BIT 2 - Resume Operation.

#define XI3c_DisableAllFEInterrupts | ( |  | BaseAddress | ) |

Value:
XI3c_WriteReg((BaseAddress), XI3C_INTR_FE_OFFSET, \
((XI3c_ReadReg(BaseAddress,XI3C_INTR_FE_OFFSET)) \
& ~(XI3C_ALL_INTR_MASK))) \
XI3C_ALL_INTR_MASK
#define XI3C_ALL_INTR_MASK
6:0 BITS
Definition: xi3c_hw.h:245
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_WriteReg
#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an I3C register.
Definition: xi3c_hw.h:292
XI3C_INTR_FE_OFFSET
#define XI3C_INTR_FE_OFFSET
Status Event Enable(Falling Edge) Register.
Definition: xi3c_hw.h:64

Disable all faling edge interrupts.

Parameters

  Base | address of the XI3c core instance.
  interrupt | mask value.

Returns
  None.

Note
  C-style signature: u16 XI3c_DisableAllFEInterrupts(XI3c *InstancePtr)

#define XI3c_DisableAllREInterrupts | ( |  | BaseAddress | ) |

Value:
XI3c_WriteReg((BaseAddress), XI3C_INTR_RE_OFFSET, \
((XI3c_ReadReg(BaseAddress,XI3C_INTR_RE_OFFSET)) \
& ~(XI3C_ALL_INTR_MASK))) \
XI3C_ALL_INTR_MASK
#define XI3C_ALL_INTR_MASK
6:0 BITS
Definition: xi3c_hw.h:245
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_WriteReg
#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an I3C register.
Definition: xi3c_hw.h:292
XI3C_INTR_RE_OFFSET
#define XI3C_INTR_RE_OFFSET
Status Event Enable(Rising Edge) Register.
Definition: xi3c_hw.h:63

Disable all raising edge interrupts.

Parameters

  Base | address of the XI3c core instance.
  interrupt | mask value.

Returns
  None.

Note
  C-style signature: u16 XI3c_DisableAllREInterrupts(XI3c *InstancePtr)

#define XI3c_DisableFEInterrupts | ( |  | BaseAddress,
|  |  | IntrMask
| ) |  |

Value:
XI3c_WriteReg((BaseAddress), XI3C_INTR_FE_OFFSET, \
((XI3c_ReadReg(BaseAddress,XI3C_INTR_FE_OFFSET)) \
& ~(IntrMask))) \
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_WriteReg
#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an I3C register.
Definition: xi3c_hw.h:292
XI3C_INTR_FE_OFFSET
#define XI3C_INTR_FE_OFFSET
Status Event Enable(Falling Edge) Register.
Definition: xi3c_hw.h:64

Disable faling edge interrupts.

Parameters

  Base | address of the XI3c core instance.
  interrupt | mask value.

Returns
  None.

Note
  C-style signature: u16 XI3c_DisableFEInterrupts(XI3c *InstancePtr, u32 IntrMask)

Referenced by XI3c_MasterInterruptHandler().

#define XI3c_DisableREInterrupts | ( |  | BaseAddress,
|  |  | IntrMask
| ) |  |

Value:
XI3c_WriteReg((BaseAddress), XI3C_INTR_RE_OFFSET, \
((XI3c_ReadReg(BaseAddress,XI3C_INTR_RE_OFFSET)) \
& ~(IntrMask))) \
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_WriteReg
#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an I3C register.
Definition: xi3c_hw.h:292
XI3C_INTR_RE_OFFSET
#define XI3C_INTR_RE_OFFSET
Status Event Enable(Rising Edge) Register.
Definition: xi3c_hw.h:63

Disable raising edge interrupts.

Parameters

  Base | address of the XI3c core instance.
  interrupt | mask value.

Returns
  None.

Note
  C-style signature: u16 XI3c_DisableREInterrupts(XI3c *InstancePtr, u32 IntrMask)

Referenced by XI3c_MasterInterruptHandler().

#define XI3c_EnableFEInterrupts | ( |  | BaseAddress,
|  |  | IntrMask
| ) |  |

Value:
XI3c_WriteReg((BaseAddress), XI3C_INTR_FE_OFFSET, \
((XI3c_ReadReg(BaseAddress, XI3C_INTR_FE_OFFSET)) | \
(IntrMask)))
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_WriteReg
#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an I3C register.
Definition: xi3c_hw.h:292
XI3C_INTR_FE_OFFSET
#define XI3C_INTR_FE_OFFSET
Status Event Enable(Falling Edge) Register.
Definition: xi3c_hw.h:64

Enable Faling edge interrupts.

Parameters

  Base | address of the XI3c core instance.
  interrupt | mask value.

Returns
  None.

Note
  C-style signature: u16 XI3c_EnableFEInterrupts(XI3c *InstancePtr, u32 IntrMask)

Referenced by XI3c_MasterSend().

#define XI3c_EnableREInterrupts | ( |  | BaseAddress,
|  |  | IntrMask
| ) |  |

Value:
XI3c_WriteReg((BaseAddress), XI3C_INTR_RE_OFFSET, \
((XI3c_ReadReg(BaseAddress, XI3C_INTR_RE_OFFSET)) | \
(IntrMask)))
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_WriteReg
#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an I3C register.
Definition: xi3c_hw.h:292
XI3C_INTR_RE_OFFSET
#define XI3C_INTR_RE_OFFSET
Status Event Enable(Rising Edge) Register.
Definition: xi3c_hw.h:63

Enable Raising edge interrupts.

Parameters

  Base | address of the XI3c core instance.
  interrupt | mask value.

Returns
  None.

Note
  C-style signature: u16 XI3c_EnableREInterrupts(XI3c *InstancePtr, u32 IntrMask)

Referenced by XI3c_CfgInitialize(), XI3c_IbiRecv(), XI3c_MasterRecv(), and XI3c_MasterSend().

#define XI3C_EVENT 0x78

Target events.

#define XI3C_FIFO_LVL_STATUS_1_OFFSET 0x34

I3C RESP & RD FIFO LVL Register.

#define XI3C_FIFO_LVL_STATUS_OFFSET 0x30

I3C CMD & WR FIFO LVL Register.

#define XI3c_FillSlaveSendCount | ( |  | InstancePtr,
|  |  | ByteCount
| ) |  |

Value:
XI3c_WriteReg((InstancePtr->Config.BaseAddress), \
XI3C_CON_RD_BYTE_COUNT, \
(((XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_CON_RD_BYTE_COUNT)) \
& (~XI3C_16BITS_MASK)) | (ByteCount & XI3C_16BITS_MASK)))
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c_WriteReg
#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an I3C register.
Definition: xi3c_hw.h:292
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778
XI3C_CON_RD_BYTE_COUNT
#define XI3C_CON_RD_BYTE_COUNT
Read byte count register.
Definition: xi3c_hw.h:87

Fill Slave send byte count value.

Parameters

  InstancePtr | is a pointer to the XI3c core instance.
  Byte | count value.

Returns
  None.

Note
  C-style signature: void XI3c_FillSlaveSendCount(XI3c *InstancePtr, u16 ByteCount)

Referenced by XI3c_SlaveSend(), and XI3c_SlaveSendPolled().

#define XI3c_GetBusIdleTime | ( |  | InstancePtr | ) |

Value:
((XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_BUS_IDLE_OFFSET)) & XI3C_18BITS_MASK)
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778
XI3C_BUS_IDLE_OFFSET
#define XI3C_BUS_IDLE_OFFSET
I3C CONTROLLER BUS IDLE Register.
Definition: xi3c_hw.h:74

Gets bus idle time of I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.

Returns
  None.

Note
  C-style signature: u32 XI3c_GetBusIdleTime(XI3c *InstancePtr)

#define XI3C_GETCAPS_REG0 0x88

Target Device Format 1 Capabilities.

#define XI3C_GETCAPS_REG1 0x8c

Target Device Format 2 Capabilities.

#define XI3c_GetDynaAddr | ( |  | InstancePtr | ) |

Value:
(XI3c_ReadReg((InstancePtr->Config.BaseAddress), XI3C_ADDRESS_OFFSET)\
& XI3C_8BITS_MASK)
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3C_ADDRESS_OFFSET
#define XI3C_ADDRESS_OFFSET
Target Address Register.
Definition: xi3c_hw.h:60
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778

Gets the dynamic address of the I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.

Returns
  None.

Note
  The address returned includes parity. C-style signature: u8 XI3c_GetDynaAddr(XI3c *InstancePtr)

#define XI3c_GetErrorStatus | ( |  | InstancePtr | ) |

Value:
(((XI3c_GetResponseData(InstancePtr)) & XI3C_RESP_CODE_MASK) \
>> XI3C_RESP_CODE_SHIFT)
XI3c_GetResponseData
#define XI3c_GetResponseData(InstancePtr)
Gets Response data of I3C.
Definition: xi3c.h:553

Gets error status from response of I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.

Returns
  0 if no error. error code if any error.

Note
  C-style signature: u32 XI3c_GetErrorStatus(XI3c *InstancePtr)

Referenced by I3cSlavePolledExample().

#define XI3c_GetMRL | ( |  | InstancePtr | ) |

Value:
(u16)((XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_MWL_MRL) >> XI3C_MRL_SHIFT) & \
XI3C_12BITS_MASK)
XI3C_MWL_MRL
#define XI3C_MWL_MRL
Maximum Write and Max Read length.
Definition: xi3c_hw.h:81
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778

Read Maximum read length.

Parameters

  InstancePtr | is a pointer to the XI3c core instance.

Returns
  Maximum read length.

Note
  C-style signature: u16 XI3c_GetMRL(XI3c *InstancePtr)

Referenced by XI3c_SlaveSend(), and XI3c_SlaveSendPolled().

#define XI3c_GetMWL | ( |  | InstancePtr | ) |

Value:
(u16)(XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_MWL_MRL) & \
XI3C_12BITS_MASK)
XI3C_MWL_MRL
#define XI3C_MWL_MRL
Maximum Write and Max Read length.
Definition: xi3c_hw.h:81
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778

Read Maximum write length.

Parameters

  InstancePtr | is a pointer to the XI3c core instance.

Returns
  Maximum write length.

Note
  C-style signature: u16 XI3c_GetMWL(XI3c *InstancePtr)

#define XI3C_GETMXDS 0x80

Target Device Max Data Speed.

#define XI3c_GetResponseData | ( |  | InstancePtr | ) |

Value:
XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_RESP_STATUS_FIFO_OFFSET)
XI3C_RESP_STATUS_FIFO_OFFSET
#define XI3C_RESP_STATUS_FIFO_OFFSET
I3C Response status FIFO Register.
Definition: xi3c_hw.h:68
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778

Gets Response data of I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.

Returns
  Response value.

Note
  C-style signature: u32 XI3c_GetResponseData(XI3c *InstancePtr)

#define XI3c_GetRevisionNumber | ( |  | InstancePtr | ) |

Value:
(((XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_VERSION_OFFSET)) & XI3C_CORE_REVISION_NUM_MASK) \
>> XI3C_CORE_REVISION_NUM_SHIFT)
XI3C_CORE_REVISION_NUM_SHIFT
#define XI3C_CORE_REVISION_NUM_SHIFT
Revision number shift.
Definition: xi3c_hw.h:102
XI3C_CORE_REVISION_NUM_MASK
#define XI3C_CORE_REVISION_NUM_MASK
BITS 15:8 - Revision number.
Definition: xi3c_hw.h:98
XI3C_VERSION_OFFSET
#define XI3C_VERSION_OFFSET
Register offsets for the XI3c device.
Definition: xi3c_hw.h:57
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778

Gets Core Revision number of I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.

Returns
  None.

Note
  C-style signature: u32 XI3c_GetRevisionNumber(XI3c *InstancePtr)

Referenced by XI3c_SetSClk().

#define XI3c_GetSclHighTime | ( |  | InstancePtr | ) |

Value:
((XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_SCL_HIGH_TIME_OFFSET)) & XI3C_18BITS_MASK)
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778
XI3C_SCL_HIGH_TIME_OFFSET
#define XI3C_SCL_HIGH_TIME_OFFSET
I3C SCL HIGH Register.
Definition: xi3c_hw.h:71

Gets scl high time of I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.

Returns
  None.

Note
  C-style signature: u32 XI3c_GetSclHighTime(XI3c *InstancePtr)

#define XI3c_GetSclLowTime | ( |  | InstancePtr | ) |

Value:
((XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_SCL_LOW_TIME_OFFSET)) & XI3C_18BITS_MASK)
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778
XI3C_SCL_LOW_TIME_OFFSET
#define XI3C_SCL_LOW_TIME_OFFSET
I3C SCL LOW Register.
Definition: xi3c_hw.h:72

Gets scl low time of I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.

Returns
  None.

Note
  C-style signature: u32 XI3c_GetSclLowTime(XI3c *InstancePtr)

#define XI3c_GetSclOdHighTime | ( |  | InstancePtr | ) |

Value:
((XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_OD_SCL_HIGH_TIME_OFFSET)) & XI3C_18BITS_MASK)
XI3C_OD_SCL_HIGH_TIME_OFFSET
#define XI3C_OD_SCL_HIGH_TIME_OFFSET
I3C OD SCL HIGH Register.
Definition: xi3c_hw.h:78
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778

Gets Scl open drain high time of I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.

Returns
  None.

Note
  C-style signature: u32 XI3c_GetSclOdHighTime(XI3c *InstancePtr)

#define XI3c_GetSclOdLowTime | ( |  | InstancePtr | ) |

Value:
((XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_OD_SCL_LOW_TIME_OFFSET)) & XI3C_18BITS_MASK)
XI3C_OD_SCL_LOW_TIME_OFFSET
#define XI3C_OD_SCL_LOW_TIME_OFFSET
I3C OD SCL LOW Register.
Definition: xi3c_hw.h:79
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778

Gets Scl open drain low time of I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.

Returns
  None.

Note
  C-style signature: u32 XI3c_GetSclOdLowTime(XI3c *InstancePtr)

#define XI3c_GetSdaHoldTime | ( |  | InstancePtr | ) |

Value:
((XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_SDA_HOLD_TIME_OFFSET)) & XI3C_18BITS_MASK)
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778
XI3C_SDA_HOLD_TIME_OFFSET
#define XI3C_SDA_HOLD_TIME_OFFSET
I3C SDA HOLD Register.
Definition: xi3c_hw.h:73

Gets sda hold time of I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.

Returns
  None.

Note
  C-style signature: u32 XI3c_GetSdaHoldTime(XI3c *InstancePtr)

#define XI3C_GETSTATUS 0x84

Target Device current Status.

#define XI3c_GetThdStartTime | ( |  | InstancePtr | ) |

Value:
((XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_THD_START_OFFSET)) & XI3C_18BITS_MASK)
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3C_THD_START_OFFSET
#define XI3C_THD_START_OFFSET
I3C START HOLD Register.
Definition: xi3c_hw.h:76
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778

This function gets Thd Start time.

Parameters

  InstancePtr | is a pointer to the XI3c instance.

Returns
  None.

Note
  C-style signature: u32 XI3c_GetThdStartTime(XI3c *InstancePtr)

#define XI3c_GetTsuStartTime | ( |  | InstancePtr | ) |

Value:
((XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_TSU_START_OFFSET)) & XI3C_18BITS_MASK)
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778
XI3C_TSU_START_OFFSET
#define XI3C_TSU_START_OFFSET
I3C START SETUP Register.
Definition: xi3c_hw.h:75

Gets Tsu Start time of I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.

Returns
  None.

Note
  C-style signature: u32 XI3c_GetTsuStartTime(XI3c *InstancePtr)

#define XI3c_GetTsuStopTime | ( |  | InstancePtr | ) |

Value:
((XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_TSU_STOP_OFFSET)) & XI3C_18BITS_MASK)
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3C_TSU_STOP_OFFSET
#define XI3C_TSU_STOP_OFFSET
I3C STOP Setup Register.
Definition: xi3c_hw.h:77
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778

Gets Tsu Stop time of I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.

Returns
  None.

Note
  C-style signature: u32 XI3c_GetTsuStopTime(XI3c *InstancePtr)

#define XI3C_H

by using protection macros

#define XI3C_HW_H_

< prevent circular inclusions

by using protection macros

#define XI3C_INTERNAL_REVISION_MASK 0x0000000F

BITS 3:0 - Internal revision.

#define XI3C_INTR_BUS_BUSY_MASK 0x00000001

BIT 0 - Bus Busy.

#define XI3C_INTR_CLK_STALL_MASK 0x00000002

BIT 1 - Clock Stall.

#define XI3C_INTR_CMD_FIFO_NOT_EMPTY_MASK 0x00002000

BIT 13 - CMD FIFO empty.

#define XI3C_INTR_CMD_FULL_MASK 0x00000004

BIT 2 - Cmd Fifo Full.

#define XI3C_INTR_CTRL_ROLE_REQUEST_MASK 0x00000200

BIT 9 - Received control role request.

#define XI3C_INTR_ERROR_TYPE_CE3_MASK 0x00000400

BIT 10 - This field will be set if there is no START coming from the new Controller that has took over the Role.

#define XI3C_INTR_FE_OFFSET 0x1C

Status Event Enable(Falling Edge) Register.

#define XI3C_INTR_HJ_MASK 0x00000100

BIT 8 - Hot join.

Referenced by XI3c_CfgInitialize(), and XI3c_MasterInterruptHandler().

#define XI3C_INTR_IBI_MASK 0x00000080

BIT 7 - IBI.

Referenced by XI3c_IbiRecv(), and XI3c_MasterInterruptHandler().

#define XI3C_INTR_RD_FIFO_ALMOST_FULL_MASK 0x00001000

BIT 12 - Read Fifo almost Full.

#define XI3C_INTR_RD_FIFO_NOT_EMPTY_MASK 0x00008000

BIT 15 - Read FIFO empty.

#define XI3C_INTR_RD_FULL_MASK 0x00000040

BIT 6 - Read Fifo Full.

Referenced by XI3c_MasterInterruptHandler(), and XI3c_MasterRecv().

#define XI3C_INTR_RE_OFFSET 0x18

Status Event Enable(Rising Edge) Register.

#define XI3C_INTR_RESP_FULL_MASK 0x00000008

BIT 3 - Resp Fifo Full.

#define XI3C_INTR_RESP_NOT_EMPTY_MASK 0x00000010

BIT 4 - Resp Fifo not empty.

Referenced by XI3c_CfgInitialize(), XI3c_IbiRecv(), XI3c_MasterInterruptHandler(), XI3c_MasterRecv(), XI3c_MasterSend(), and XI3c_SlaveInterruptHandler().

#define XI3C_INTR_RETURN_ROLE_REQ_ACK_MASK 0x00000800

BIT 11 - Received ACK on controller role request back.

#define XI3C_INTR_STATUS_OFFSET 0x14

Status Event Register.

Referenced by XI3c_MasterInterruptHandler(), and XI3c_SlaveInterruptHandler().

#define XI3C_INTR_WR_FIFO_ALMOST_FULL_MASK 0x00000020

BIT 5 - Write Fifo Full.

Referenced by XI3c_MasterInterruptHandler(), and XI3c_MasterSend().

#define XI3C_INTR_WR_FIFO_NOT_EMPTY_MASK 0x00004000

BIT 14 - Write FIFO empty.

#define XI3c_IsDyncAddrAssigned | ( |  | InstancePtr | ) |

Value:
((XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_SR_OFFSET)) & XI3C_SR_SLV_DYNC_ADDR_DONE_MASK)
XI3C_SR_OFFSET
#define XI3C_SR_OFFSET
Status Register.
Definition: xi3c_hw.h:61
XI3C_SR_SLV_DYNC_ADDR_DONE_MASK
#define XI3C_SR_SLV_DYNC_ADDR_DONE_MASK
BIT 19 - Dynamic address assigned to slave.
Definition: xi3c_hw.h:153
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778

Check the dynamic address assignment status of I3C in slave mode.

Parameters

  InstancePtr | is a pointer to the XI3c instance.

Returns
  1 if address assigned. 0 if address not assigned.

Note
  C-style signature: u32 XI3c_IsDyncAddrAssigned(XI3c *InstancePtr)

Referenced by I3cSlaveIntrExample(), and I3cSlavePolledExample().

#define XI3c_IsRespAvailable | ( |  | InstancePtr | ) |

Value:
((XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_SR_OFFSET)) & XI3C_SR_RESP_NOT_EMPTY_MASK)
XI3C_SR_OFFSET
#define XI3C_SR_OFFSET
Status Register.
Definition: xi3c_hw.h:61
XI3C_SR_RESP_NOT_EMPTY_MASK
#define XI3C_SR_RESP_NOT_EMPTY_MASK
BIT 4 - Resp Fifo not empty.
Definition: xi3c_hw.h:137
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778

Check the response status of I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.

Returns
  1 if response available. 0 if response not available.

Note
  C-style signature: u32 XI3c_IsRespAvailable(XI3c *InstancePtr)

Referenced by I3cSlavePolledExample().

#define XI3C_MWL_MRL 0x74

Maximum Write and Max Read length.

#define XI3C_OD_SCL_HIGH_TIME_OFFSET 0x54

I3C OD SCL HIGH Register.

Referenced by XI3c_SetSClk().

#define XI3C_OD_SCL_LOW_TIME_OFFSET 0x58

I3C OD SCL LOW Register.

Referenced by XI3c_SetSClk().

#define XI3C_RD_FIFO_OFFSET 0x28

I3C Read Data FIFO Register.

Referenced by XI3c_ReadRxFifo().

#define XI3C_RD_FIFO_RESET_MASK 0x00000008

BIT 3 - Read fifo reset.

#define XI3c_RdFifoLevel | ( |  | InstancePtr | ) |

Value:
(u16)(XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_FIFO_LVL_STATUS_1_OFFSET) & \
XI3C_16BITS_MASK)
XI3C_FIFO_LVL_STATUS_1_OFFSET
#define XI3C_FIFO_LVL_STATUS_1_OFFSET
I3C RESP &amp; RD FIFO LVL Register.
Definition: xi3c_hw.h:70
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778

Read RD FIFO LEVEL.

Parameters

  InstancePtr | is a pointer to the XI3c core instance.

Returns
  None.

Note
  C-style signature: u16 XI3c_RdFifoLevel(XI3c *InstancePtr)

Referenced by XI3c_IbiRecvPolled(), XI3c_MasterInterruptHandler(), and XI3c_MasterRecvPolled().

#define XI3c_ReadReg | ( |  | BaseAddress,
|  |  | RegOffset
| ) |  | XI3c_In32((BaseAddress) + (u32)(RegOffset))

Read an I3C register.

Parameters

  BaseAddress | contains the base address of the device.
  RegOffset | contains the offset from the 1st register of the device to select the specific register.

Returns
  The value read from the register.

Note
  C-Style signature: u32 XI3c_ReadReg(u32 BaseAddress. int RegOffset)

Referenced by XI3c_MasterInterruptHandler(), XI3c_ReadRxFifo(), and XI3c_SlaveInterruptHandler().

#define XI3C_RESET_OFFSET 0x04

Soft Reset Register.

#define XI3C_RESP_FIFO_RESET_MASK 0x00000010

BIT 4 - Response fifo reset.

#define XI3C_RESP_STATUS_FIFO_OFFSET 0x2C

I3C Response status FIFO Register.

Referenced by XI3c_MasterInterruptHandler().

#define XI3c_RespFifoLevel | ( |  | InstancePtr | ) |

Value:
(u16)((XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_FIFO_LVL_STATUS_1_OFFSET) & \
XI3C_MSB_16BITS_MASK) >> XI3C_RESP_LVL_SHIFT)
XI3C_FIFO_LVL_STATUS_1_OFFSET
#define XI3C_FIFO_LVL_STATUS_1_OFFSET
I3C RESP &amp; RD FIFO LVL Register.
Definition: xi3c_hw.h:70
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778

Read RESP FIFO LEVEL.

Parameters

  InstancePtr | is a pointer to the XI3c core instance.

Returns
  None.

Note
  C-style signature: u16 XI3c_RespFifoLevel(XI3c *InstancePtr)

#define XI3c_RespFifoNotEmpty | ( |  | InstancePtr | ) |

Value:
(u32)(XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_SR_OFFSET) & \
XI3C_SR_RESP_NOT_EMPTY_MASK)
XI3C_SR_OFFSET
#define XI3C_SR_OFFSET
Status Register.
Definition: xi3c_hw.h:61
XI3C_SR_RESP_NOT_EMPTY_MASK
#define XI3C_SR_RESP_NOT_EMPTY_MASK
BIT 4 - Resp Fifo not empty.
Definition: xi3c_hw.h:137
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778

Check Response FIFO empty status.

Parameters

  InstancePtr | is a pointer to the XI3c core instance.

Returns
  None.

Note
  C-style signature: u32 XI3c_RespFifoNotEmpty(XI3c *InstancePtr)

Referenced by XI3c_IbiRecvPolled(), and XI3c_MasterInterruptHandler().

#define XI3c_RxFifoNotEmpty | ( |  | InstancePtr | ) |

Value:
(u32)(XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_SR_OFFSET) & \
XI3C_SR_RD_FIFO_NOT_EMPTY_MASK)
XI3C_SR_OFFSET
#define XI3C_SR_OFFSET
Status Register.
Definition: xi3c_hw.h:61
XI3C_SR_RD_FIFO_NOT_EMPTY_MASK
#define XI3C_SR_RD_FIFO_NOT_EMPTY_MASK
BIT 15 - Read FIFO empty.
Definition: xi3c_hw.h:152
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778

Check Read FIFO empty status.

Parameters

  InstancePtr | is a pointer to the XI3c core instance.

Returns
  None.

Note
  C-style signature: u32 XI3c_RxFifoNotEmpty(XI3c *InstancePtr)

Referenced by XI3c_IbiRecvPolled(), and XI3c_MasterInterruptHandler().

#define XI3C_SCL_HIGH_TIME_OFFSET 0x38

I3C SCL HIGH Register.

Referenced by XI3c_SetSClk().

#define XI3C_SCL_LOW_TIME_OFFSET 0x3C

I3C SCL LOW Register.

Referenced by XI3c_SetSClk().

#define XI3C_SDA_HOLD_TIME_OFFSET 0x40

I3C SDA HOLD Register.

Referenced by XI3c_SetSClk().

#define XI3c_SetBusIdleTime | ( |  | InstancePtr,
|  |  | Val
| ) |  |

Value:
XI3c_WriteReg(InstancePtr->Config.BaseAddress, XI3C_BUS_IDLE_OFFSET,\
(Val & XI3C_18BITS_MASK))
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c_WriteReg
#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an I3C register.
Definition: xi3c_hw.h:292
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778
XI3C_BUS_IDLE_OFFSET
#define XI3C_BUS_IDLE_OFFSET
I3C CONTROLLER BUS IDLE Register.
Definition: xi3c_hw.h:74

Sets bus idle time of I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  Val | is bus idle time value to be set.

Returns
  None.

Note
  Caller need to update other timing parameters if required. C-style signature: void XI3c_SetBusIdleTime(XI3c *InstancePtr, u32 Val)

#define XI3c_SetCapsFormat1 | ( |  | InstancePtr,
|  |  | Cap1,
|  |  | Cap2,
|  |  | Cap3,
|  |  | Cap4
| ) |  |

Value:
XI3c_WriteReg(InstancePtr->Config.BaseAddress, \
XI3C_GETCAPS_REG0, \
(((Caps4 & XI3C_8BITS_MASK) << XI3C_CAPS4_SHIFT) |\
((Caps3 & XI3C_8BITS_MASK) << XI3C_CAPS3_SHIFT) | \
((Caps2 & XI3C_8BITS_MASK) << XI3C_CAPS2_SHIFT) | \
(Caps1 & XI3C_8BITS_MASK)))
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c_WriteReg
#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an I3C register.
Definition: xi3c_hw.h:292
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778
XI3C_GETCAPS_REG0
#define XI3C_GETCAPS_REG0
Target Device Format 1 Capabilities.
Definition: xi3c_hw.h:85

Sets device capabilities format1.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  Caps1 | of target device.
  Caps2 | of target device.
  Caps3 | of target device.
  Caps4 | of target device.

Returns
  None.

Note
  C-style signature: void XI3c_SetCapsFormat1(XI3c *InstancePtr, u8 Cap1, u8 Cap2, u8 Cap3, u8 Cap4)

#define XI3c_SetCapsFormat2 | ( |  | InstancePtr,
|  |  | Cap1,
|  |  | Cap2
| ) |  |

Value:
XI3c_WriteReg(InstancePtr->Config.BaseAddress, \
XI3C_GETCAPS_REG1, \
(((Caps2 & XI3C_8BITS_MASK) << XI3C_CAPS2_SHIFT) |\
(Caps1 & XI3C_8BITS_MASK)))
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c_WriteReg
#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an I3C register.
Definition: xi3c_hw.h:292
XI3C_GETCAPS_REG1
#define XI3C_GETCAPS_REG1
Target Device Format 2 Capabilities.
Definition: xi3c_hw.h:86
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778

Sets device capabilities format2.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  Caps1 | of target device.
  Caps2 | of target device.

Returns
  None.

Note
  C-style signature: void XI3c_SetCapsFormat2(XI3c *InstancePtr, u8 Cap1, u8 Cap2)

#define XI3c_SetDeviceStatus | ( |  | InstancePtr,
|  |  | Format1,
|  |  | Format2
| ) |  |

Value:
XI3c_WriteReg(InstancePtr->Config.BaseAddress, \
XI3C_GETSTATUS, \
((Format1 & XI3C_16BITS_MASK) | \
((Format2 & XI3C_16BITS_MASK) << \
XI3C_GETSTATUS_FORMAT2_SHIFT)))
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c_WriteReg
#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an I3C register.
Definition: xi3c_hw.h:292
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778
XI3C_GETSTATUS
#define XI3C_GETSTATUS
Target Device current Status.
Definition: xi3c_hw.h:84

Sets device status of I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  Format1 | value of Device status.
  Format2 | value of Device status.

Returns
  None.

Note
  C-style signature: void XI3c_SetDeviceStatus(XI3c *InstancePtr, u16 Format1, u16 Format2)

#define XI3c_SetMaxDataSpeed | ( |  | InstancePtr,
|  |  | Format1,
|  |  | Format3
| ) |  |

Value:
XI3c_WriteReg(InstancePtr->Config.BaseAddress, \
XI3C_GETMXDS, \
((Format1 & XI3C_16BITS_MASK) | \
((Format3 & XI3C_8BITS_MASK) << \
XI3C_GETMXDS_FORMAT3_DATA_SHIFT)))
XI3C_GETMXDS
#define XI3C_GETMXDS
Target Device Max Data Speed.
Definition: xi3c_hw.h:83
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c_WriteReg
#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an I3C register.
Definition: xi3c_hw.h:292
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778

Sets device Max data speed.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  Format1 | value of Device status.
  Format3 | value of Device status.

Returns
  None.

Note
  C-style signature: void XI3c_SetMaxDataSpeed(XI3c *InstancePtr, u16 Format1, u8 Format3)

#define XI3c_SetSclHighTime | ( |  | InstancePtr,
|  |  | Val
| ) |  |

Value:
XI3c_WriteReg(InstancePtr->Config.BaseAddress, \
XI3C_SCL_HIGH_TIME_OFFSET, \
(Val & XI3C_18BITS_MASK))
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c_WriteReg
#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an I3C register.
Definition: xi3c_hw.h:292
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778
XI3C_SCL_HIGH_TIME_OFFSET
#define XI3C_SCL_HIGH_TIME_OFFSET
I3C SCL HIGH Register.
Definition: xi3c_hw.h:71

Sets scl high time of I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  Val | is scl high time value to be set.

Returns
  None.

Note
  Caller need to update other timing parameters if required. C-style signature: void XI3c_SetSclHighTime(XI3c *InstancePtr, u32 Val)

#define XI3c_SetSclLowTime | ( |  | InstancePtr,
|  |  | Val
| ) |  |

Value:
XI3c_WriteReg(InstancePtr->Config.BaseAddress, \
XI3C_SCL_LOW_TIME_OFFSET, \
(Val & XI3C_18BITS_MASK))
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c_WriteReg
#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an I3C register.
Definition: xi3c_hw.h:292
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778
XI3C_SCL_LOW_TIME_OFFSET
#define XI3C_SCL_LOW_TIME_OFFSET
I3C SCL LOW Register.
Definition: xi3c_hw.h:72

Sets scl low time of I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  Val | is scl low time value to be set.

Returns
  None.

Note
  Caller need to update other timing parameters if required. C-style signature: void XI3c_SetSclLowTime(XI3c *InstancePtr, u32 Val)

#define XI3c_SetSclOdHighTime | ( |  | InstancePtr,
|  |  | Val
| ) |  |

Value:
XI3c_WriteReg(InstancePtr->Config.BaseAddress, \
XI3C_OD_SCL_HIGH_TIME_OFFSET, \
(Val & XI3C_18BITS_MASK))
XI3C_OD_SCL_HIGH_TIME_OFFSET
#define XI3C_OD_SCL_HIGH_TIME_OFFSET
I3C OD SCL HIGH Register.
Definition: xi3c_hw.h:78
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c_WriteReg
#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an I3C register.
Definition: xi3c_hw.h:292
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778

Sets Scl open drain high time of I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  Val | is Scl open drain high time value to be set.

Returns
  None.

Note
  Caller need to update other timing parameters if required. C-style signature: void XI3c_SetSclOdHighTime(XI3c *InstancePtr, u32 Val)

#define XI3c_SetSclOdLowTime | ( |  | InstancePtr,
|  |  | Val
| ) |  |

Value:
XI3c_WriteReg(InstancePtr->Config.BaseAddress, \
XI3C_OD_SCL_LOW_TIME_OFFSET, \
(Val & XI3C_18BITS_MASK))
XI3C_OD_SCL_LOW_TIME_OFFSET
#define XI3C_OD_SCL_LOW_TIME_OFFSET
I3C OD SCL LOW Register.
Definition: xi3c_hw.h:79
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c_WriteReg
#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an I3C register.
Definition: xi3c_hw.h:292
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778

Sets Scl open drain low time of I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  Val | is Scl open drain low time value to be set.

Returns
  None.

Note
  Caller need to update other timing parameters if required. C-style signature: void XI3c_SetSclOdLowTime(XI3c *InstancePtr, u32 Val)

#define XI3c_SetSdaHoldTime | ( |  | InstancePtr,
|  |  | Val
| ) |  |

Value:
XI3c_WriteReg(InstancePtr->Config.BaseAddress, \
XI3C_SDA_HOLD_TIME_OFFSET, \
(Val & XI3C_18BITS_MASK))
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c_WriteReg
#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an I3C register.
Definition: xi3c_hw.h:292
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778
XI3C_SDA_HOLD_TIME_OFFSET
#define XI3C_SDA_HOLD_TIME_OFFSET
I3C SDA HOLD Register.
Definition: xi3c_hw.h:73

Sets sda hold time of I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  Val | is sda hold time value to be set.

Returns
  None.

Note
  Caller need to update other timing parameters if required. C-style signature: void XI3c_SetSdaHoldTime(XI3c *InstancePtr, u32 Val)

#define XI3c_SetThdStartTime | ( |  | InstancePtr,
|  |  | Val
| ) |  |

Value:
XI3c_WriteReg(InstancePtr->Config.BaseAddress, XI3C_THD_START_OFFSET,\
(Val & XI3C_18BITS_MASK))
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3C_THD_START_OFFSET
#define XI3C_THD_START_OFFSET
I3C START HOLD Register.
Definition: xi3c_hw.h:76
XI3c_WriteReg
#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an I3C register.
Definition: xi3c_hw.h:292
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778

Sets Thd Start time of I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  Val | is Thd Start time value to be set.

Returns
  None.

Note
  Caller need to update other timing parameters if required. C-style signature: void XI3c_SetThdStartTime(XI3c *InstancePtr, u32 Val)

#define XI3c_SetTsuStartTime | ( |  | InstancePtr,
|  |  | Val
| ) |  |

Value:
XI3c_WriteReg(InstancePtr->Config.BaseAddress, XI3C_TSU_START_OFFSET,\
(Val & XI3C_18BITS_MASK))
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c_WriteReg
#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an I3C register.
Definition: xi3c_hw.h:292
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778
XI3C_TSU_START_OFFSET
#define XI3C_TSU_START_OFFSET
I3C START SETUP Register.
Definition: xi3c_hw.h:75

Sets Tsu Start time of I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  Val | is Tsu Start time value to be set.

Returns
  None.

Note
  Caller need to update other timing parameters if required. C-style signature: void XI3c_SetTsuStartTime(XI3c *InstancePtr, u32 Val)

#define XI3c_SetTsuStopTime | ( |  | InstancePtr,
|  |  | Val
| ) |  |

Value:
XI3c_WriteReg(InstancePtr->Config.BaseAddress, XI3C_TSU_STOP_OFFSET,\
(Val & XI3C_18BITS_MASK))
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3C_TSU_STOP_OFFSET
#define XI3C_TSU_STOP_OFFSET
I3C STOP Setup Register.
Definition: xi3c_hw.h:77
XI3c_WriteReg
#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an I3C register.
Definition: xi3c_hw.h:292
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778

Sets Tsu Stop time of I3C.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  Val | is Tsu Stop time value to be set.

Returns
  None.

Note
  Caller need to update other timing parameters if required. C-style signature: void XI3c_SetTsuStopTime(XI3c *InstancePtr, u32 Val)

#define XI3C_SOFT_RESET_MASK 0x00000001

BIT 0 - Reset.

#define XI3C_SR_BUS_BUSY_MASK 0x00000001

BIT 0 - Bus Busy.

#define XI3C_SR_BUS_BUSY_SHIFT 0

BIT 0 - Bus Busy.

#define XI3C_SR_CLK_STALL_MASK 0x00000002

BIT 1 - Clock Stall.

#define XI3C_SR_CLK_STALL_SHIFT 1

BIT 1 - Clock Stall.

#define XI3C_SR_CMD_FIFO_NOT_EMPTY_MASK 0x00002000

BIT 13 - CMD FIFO empty.

#define XI3C_SR_CMD_FULL_MASK 0x00000004

BIT 2 - Cmd Fifo Full.

#define XI3C_SR_CMD_FULL_SHIFT 2

BIT 2 - Cmd Fifo Full.

#define XI3C_SR_CTRL_ROLE_REQUEST_MASK 0x00000200

BIT 9 - Received control role request.

#define XI3C_SR_ERROR_TYPE_CE3_MASK 0x00000400

BIT 10 - This field will be set if there is no START coming from the new Controller that has took over the Role.

#define XI3C_SR_HJ_MASK 0x00000100

BIT 8 - Hot join.

#define XI3C_SR_IBI_MASK 0x00000080

BIT 7 - IBI.

#define XI3C_SR_OFFSET 0x10

Status Register.

Referenced by XI3c_IbiRecvPolled().

#define XI3C_SR_RD_FIFO_ALMOST_FULL_MASK 0x00001000

BIT 12 - Read Fifo almost Full.

#define XI3C_SR_RD_FIFO_NOT_EMPTY_MASK 0x00008000

BIT 15 - Read FIFO empty.

Referenced by XI3c_IbiRecvPolled().

#define XI3C_SR_RD_FULL_MASK 0x00000040

BIT 6 - Read Fifo Full.

#define XI3C_SR_RD_FULL_SHIFT 6

BIT 6 - Read Fifo Full.

#define XI3C_SR_RESP_FULL_MASK 0x00000008

BIT 3 - Resp Fifo Full.

#define XI3C_SR_RESP_FULL_SHIFT 3

BIT 3 - Resp Fifo Full.

#define XI3C_SR_RESP_NOT_EMPTY_MASK 0x00000010

BIT 4 - Resp Fifo not empty.

#define XI3C_SR_RESP_NOT_EMPTY_SHIFT 4

BIT 4 - Resp Fifo not empty.

#define XI3C_SR_RETURN_ROLE_REQ_ACK_MASK 0x00000800

BIT 11 - Received ACK on controller role request back.

#define XI3C_SR_SLV_DYNC_ADDR_DONE_MASK 0x00080000

BIT 19 - Dynamic address assigned to slave.

#define XI3C_SR_SLV_DYNC_ADDR_DONE_SHIFT 19

BIT 19 - Dynamic address assigned to slave.

#define XI3C_SR_WR_FIFO_NOT_EMPTY_MASK 0x00004000

BIT 14 - Write FIFO empty.

#define XI3C_SR_WR_FULL_MASK 0x00000020

BIT 5 - Write Fifo Full.

#define XI3C_SR_WR_FULL_SHIFT 5

BIT 5 - Write Fifo Full.

#define XI3C_TARGET_ADDR_BCR 0x60

I3C Target dynamic Address and BCR Register.

#define XI3C_THD_START_OFFSET 0x4C

I3C START HOLD Register.

Referenced by XI3c_SetSClk().

#define XI3C_TSU_START_OFFSET 0x48

I3C START SETUP Register.

Referenced by XI3c_SetSClk().

#define XI3C_TSU_STOP_OFFSET 0x50

I3C STOP Setup Register.

Referenced by XI3c_SetSClk().

#define XI3C_VERSION_OFFSET 0x00

Register offsets for the XI3c device.

Version Register

#define XI3C_WR_FIFO_OFFSET 0x24

I3C Write Data FIFO Register.

Referenced by XI3c_WriteTxFifo().

#define XI3C_WR_FIFO_RESET_MASK 0x00000004

BIT 2 - Write fifo reset.

#define XI3c_WrFifoLevel | ( |  | InstancePtr | ) |

Value:
(u16)(XI3c_ReadReg(InstancePtr->Config.BaseAddress, \
XI3C_FIFO_LVL_STATUS_OFFSET) & XI3C_16BITS_MASK)
XI3c_ReadReg
#define XI3c_ReadReg(BaseAddress, RegOffset)
Read an I3C register.
Definition: xi3c_hw.h:274
XI3c_Config::BaseAddress
UINTPTR BaseAddress
Base address of the device.
Definition: xi3c.h:735
XI3c::Config
XI3c_Config Config
Configuration structure.
Definition: xi3c.h:778
XI3C_FIFO_LVL_STATUS_OFFSET
#define XI3C_FIFO_LVL_STATUS_OFFSET
I3C CMD &amp; WR FIFO LVL Register.
Definition: xi3c_hw.h:69

Read WR FIFO LEVEL.

Parameters

  InstancePtr | is the instance of I3C

Returns
  None.

Note
  C-Style signature: void XI3c_WrFifoLevel(XI3cPsx *InstancePtr)

Referenced by XI3c_MasterInterruptHandler(), XI3c_MasterSend(), XI3c_MasterSendPolled(), XI3c_SlaveSend(), and XI3c_SlaveSendPolled().

#define XI3c_WriteReg | ( |  | BaseAddress,
|  |  | RegOffset,
|  |  | RegisterValue
| ) |  | XI3c_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))

Write an I3C register.

Parameters

  BaseAddress | contains the base address of the device.
  RegOffset | contains the offset from the 1st register of the device to select the specific register.
  RegisterValue | is the value to be written to the register.

Returns
  None.

Note
  C-Style signature: void XI3c_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue)

Referenced by XI3c_FillCmdFifo(), XI3c_MasterInterruptHandler(), XI3c_SetSClk(), XI3c_SlaveInterruptHandler(), and XI3c_WriteTxFifo().

## Typedef Documentation

typedef void(* XI3c_IntrHandler)(u32 StatusEvent)

The handler data type allows the user to define a callback function to respond to interrupt events in the system.

This function is executed in interrupt context, so amount of processing should be minimized.

Parameters

  CallBackRef | is the callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. Its type is not important to the driver, so it is a void pointer.
  StatusEvent | indicates one or more status events that occurred.

## Function Documentation

void XI3C_BusInit | ( | XI3c * | InstancePtr | ) |

Initializes the XI3c slaves devices by disable/enable events and reset dynamic addresses.

Parameters

  InstancePtr | is a pointer to the XI3c instance.

Returns
  None.

Note
  None.

< SDR mode

< SDR mode

< SDR mode

References XI3c_SendTransferCmd().

Referenced by I3cMasterDaaExample(), I3cMasterIntrExample(), I3cMasterPolledExample(), and XI3c_CfgInitialize().

s32 XI3c_CfgInitialize | ( | XI3c * | InstancePtr,
|  | XI3c_Config * | ConfigPtr,
|  | u32 | EffectiveAddr
| ) |  |

Initializes a specific XI3c instance such that the driver is ready to use.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  ConfigPtr | is a reference to a structure containing information about a specific I3C device. This function initializes an InstancePtr object for a specific device specified by the contents of Config.
  EffectiveAddr | is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use ConfigPtr->BaseAddress for this parameter, passing the physical address instead.

Returns
  The return value is XST_SUCCESS if successful.

Note
  None.

< Master mode

< Slave mode

References XI3c_Config::BaseAddress, XI3c::Config, XI3c::CurDeviceCount, XI3c_Config::DeviceCount, XI3c_Config::DeviceId, XI3c_Config::DeviceRole, XI3c_Config::HjCapable, XI3c_Config::IbiCapable, XI3c_Config::InputClockHz, XI3c::IsReady, XI3c_Config::RwFifoDepth, XI3c_Config::WrThreshold, XI3C_BusInit(), XI3c_ConfigIbi(), XI3c_DynaAddrAssign(), XI3c_EnableREInterrupts, XI3C_INTR_HJ_MASK, and XI3C_INTR_RESP_NOT_EMPTY_MASK.

Referenced by I3cMasterDaaExample(), I3cMasterIntrExample(), I3cMasterPolledExample(), I3cSlaveIntrExample(), and I3cSlavePolledExample().

void XI3c_ConfigIbi | ( | XI3c * | InstancePtr,
|  | u8 | DevCount
| ) |  |

This configure target address and BCR register values of available devices to the controller RAM.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  DevCount | is the number of slave devices present.

Returns
  None.

Note
  None.

References XI3c::IsReady.

Referenced by XI3c_CfgInitialize().

s32 XI3c_DynaAddrAssign | ( | XI3c * | InstancePtr,
|  | u8 | DynaAddr[],
|  | u8 | DevCount
| ) |  |

This function sends dynamic Address Assignment for available devices.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  DynaAddr | is an array of dynamic addresses.
  DevCount | is the number of slave devices present.

Returns
  - XST_SUCCESS if everything went well.
  - XST_FAILURE if any error.

Note
  None.

< Enable repeated start

< Broadcast address

< BCR - RecvBuffer[6]

< DCR - RecvBuffer[7]

< Dynamic address

References XI3c_SlaveInfo::Bcr, XI3c::CurDeviceCount, XI3c_SlaveInfo::Dcr, XI3c_SlaveInfo::DynaAddr, XI3c_SlaveInfo::Id, XI3c::IsReady, XI3c::SendBufferPtr, XI3c::SendByteCount, XI3c_MasterRecvPolled(), XI3c_SendTransferCmd(), XI3c::XI3c_SlaveInfoTable, and XI3c_WriteTxFifo().

Referenced by I3cMasterDaaExample(), XI3c_CfgInitialize(), and XI3c_MasterInterruptHandler().

void XI3c_FillCmdFifo | ( | XI3c * | InstancePtr,
|  | XI3c_Cmd * | Cmd
| ) |  |

Fill I3C Command fifo.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  TransferCmd | is a pointer to the XI3c_Cmd instance.

Returns
  None.

Note
  None.

< Command Type: 0 to 3 bits

< Repeated start or Termination on Completion: 4th bit

< Parity Error Check: 5th bit

< RW: 8th bit + Device address: 9 to 15 bits

< No.of bytes R/W to/from R/W FIFOs

< Transaction ID

References XI3c_Config::BaseAddress, XI3c::Config, XI3C_CMD_FIFO_OFFSET, and XI3c_WriteReg.

Referenced by XI3c_MasterRecv(), XI3c_MasterRecvPolled(), XI3c_MasterSend(), XI3c_MasterSendPolled(), and XI3c_SendTransferCmd().

s32 XI3c_IbiRecv | ( | XI3c * | InstancePtr,
|  | u8 * | MsgPtr
| ) |  |

This function setup for receive during IBI in interrupt mode.

It enables the required interrupts for performing read operation during IBI.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  MsgPtr | is the pointer to the recv buffer.

Returns
  - XST_SUCCESS if everything went well.
  - XST_NO_DATA if message buffer is NULL.

Note
  None.

References XI3c_Config::BaseAddress, XI3c::Config, XI3c::RecvBufferPtr, XI3c_EnableREInterrupts, XI3C_INTR_IBI_MASK, and XI3C_INTR_RESP_NOT_EMPTY_MASK.

s32 XI3c_IbiRecvPolled | ( | XI3c * | InstancePtr,
|  | u8 * | MsgPtr
| ) |  |

This function receives data during IBI in polled mode.

It polls the data register for data to come in during IBI. If master fails to read data due to any error, it will return with status.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  MsgPtr | is the pointer to the recv buffer.

Returns
  - XST_SUCCESS if everything went well.
  - XST_RECV_ERROR if any error.

Note
  None.

References XI3c_Config::BaseAddress, XI3c::Config, XI3c::RecvBufferPtr, XI3c::RecvByteCount, TIMEOUT_COUNTER, XI3c_RdFifoLevel, XI3c_ReadRxFifo(), XI3c_RespFifoNotEmpty, XI3c_RxFifoNotEmpty, XI3C_SR_OFFSET, and XI3C_SR_RD_FIFO_NOT_EMPTY_MASK.

XI3c_Config* XI3c_LookupConfig | ( | u16 | DeviceId | ) |

Looks up the device configuration based on the unique device ID.

A table contains the configuration info for each device in the system.

Parameters

  DeviceId | contains the ID of the device to look up the configuration for.

Returns
  A pointer to the configuration found or NULL if the specified device ID was not found. See xi3c.h for the definition of XI3c_Config.

Note
  None.

References XI3c_ConfigTable.

Referenced by I3cMasterDaaExample(), I3cMasterIntrExample(), I3cMasterPolledExample(), I3cSlaveIntrExample(), and I3cSlavePolledExample().

void XI3c_MasterInterruptHandler | ( | XI3c * | InstancePtr | ) |

The interrupt handler for the master mode.

It does the protocol handling for the interrupt-driven transfers.

If the Master is receiving data then the data is read from the FIFO and the Master has to request for more data (if there is more data to receive). If all the data has been received then a completion event is signalled to the upper layer by calling the callback handler. It is an error if the amount of received data is more than expected.

Parameters

  InstancePtr | is a pointer to the XI3c instance.

Returns
  None.

Note
  None.

References XI3c_Config::BaseAddress, XI3c::Config, XI3c::CurDeviceCount, XI3c::Error, XI3c_Config::IbiCapable, XI3c::RecvByteCount, XI3c::SendByteCount, XI3c::StatusHandler, XI3c_DisableFEInterrupts, XI3c_DisableREInterrupts, XI3c_DynaAddrAssign(), XI3C_INTR_HJ_MASK, XI3C_INTR_IBI_MASK, XI3C_INTR_RD_FULL_MASK, XI3C_INTR_RESP_NOT_EMPTY_MASK, XI3C_INTR_STATUS_OFFSET, XI3C_INTR_WR_FIFO_ALMOST_FULL_MASK, XI3c_RdFifoLevel, XI3c_ReadReg, XI3c_ReadRxFifo(), XI3C_RESP_STATUS_FIFO_OFFSET, XI3c_RespFifoNotEmpty, XI3c_RxFifoNotEmpty, XI3c_WrFifoLevel, XI3c_WriteReg, and XI3c_WriteTxFifo().

Referenced by I3cMasterIntrExample().

s32 XI3c_MasterRecv | ( | XI3c * | InstancePtr,
|  | XI3c_Cmd * | Cmd,
|  | u8 * | MsgPtr,
|  | u16 | ByteCount
| ) |  |

This function initiates a interrupt mode receive in master mode.

It sets the transfer size register so the slave can send data to us. The rest of the work is managed by interrupt handler.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  Cmd | is a pointer to the XI3c_Cmd instance.
  MsgPtr | is the pointer to the recv buffer.
  ByteCount | is the number of bytes to be recv.

Returns
  None.

Note
  None.

< Controller uses byte count during bus transaction

< Read operation

References XI3c_Config::BaseAddress, XI3c::Config, XI3c::RecvBufferPtr, XI3c::RecvByteCount, XI3c_EnableREInterrupts, XI3c_FillCmdFifo(), XI3C_INTR_RD_FULL_MASK, and XI3C_INTR_RESP_NOT_EMPTY_MASK.

Referenced by I3cMasterIntrExample().

s32 XI3c_MasterRecvPolled | ( | XI3c * | InstancePtr,
|  | XI3c_Cmd * | Cmd,
|  | u8 * | MsgPtr,
|  | u16 | ByteCount
| ) |  |

This function initiates a polled mode receive in master mode.

It repeatedly sets the transfer size register so the slave can send data to us. It polls the data register for data to come in. If master fails to read data due arbitration lost or any other error, will return with status.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  Cmd | is a pointer to the XI3c_Cmd instance.
  MsgPtr | is the pointer to the send buffer.
  ByteCount | is the number of bytes to be sent.

Returns
  - XST_SUCCESS if everything went well.
  - XST_RECV_ERROR if any error.

Note
  None.

< DAA case

< Controller uses byte count during bus transaction

< Read operation

References XI3c::RecvBufferPtr, XI3c::RecvByteCount, XI3c_FillCmdFifo(), XI3c_RdFifoLevel, and XI3c_ReadRxFifo().

Referenced by I3cMasterDaaExample(), I3cMasterPolledExample(), and XI3c_DynaAddrAssign().

s32 XI3c_MasterSend | ( | XI3c * | InstancePtr,
|  | XI3c_Cmd * | Cmd,
|  | u8 * | MsgPtr,
|  | u16 | ByteCount
| ) |  |

This function initiates a interrupt mode send in master mode.

It sends data to the FIFO and waits for the slave to pick them up. If master fails to send data due arbitration lost or any other, will stop transfer with status.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  Cmd | is a pointer to the XI3c_Cmd instance.
  MsgPtr | is the pointer to the send buffer.
  ByteCount | is the number of bytes to be sent.

Returns
  None.

Note
  None.

< Controller uses byte count during bus transaction

< Write operation

References XI3c_Config::BaseAddress, XI3c::Config, XI3c::SendBufferPtr, XI3c::SendByteCount, XI3c_Config::WrThreshold, XI3c_EnableFEInterrupts, XI3c_EnableREInterrupts, XI3c_FillCmdFifo(), XI3C_INTR_RESP_NOT_EMPTY_MASK, XI3C_INTR_WR_FIFO_ALMOST_FULL_MASK, XI3c_WrFifoLevel, and XI3c_WriteTxFifo().

Referenced by I3cMasterIntrExample().

s32 XI3c_MasterSendPolled | ( | XI3c * | InstancePtr,
|  | XI3c_Cmd * | Cmd,
|  | u8 * | MsgPtr,
|  | u16 | ByteCount
| ) |  |

This function initiates a polled mode send in master mode.

It sends data to the FIFO and waits for the slave to pick them up. If master fails to send data due arbitration lost or any other error, will stop transfer status.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  Cmd | is a pointer to the XI3c_Cmd instance.
  MsgPtr | is the pointer to the send buffer.
  ByteCount | is the number of bytes to be sent.

Returns
  - XST_SUCCESS if everything went well.
  - XST_SEND_ERROR if any error.

Note
  None.

< Controller uses byte count during bus transaction

< Write operation

References XI3c::SendBufferPtr, XI3c::SendByteCount, XI3c_FillCmdFifo(), XI3c_WrFifoLevel, and XI3c_WriteTxFifo().

Referenced by I3cMasterDaaExample(), and I3cMasterPolledExample().

void XI3c_ReadRxFifo | ( | XI3c * | InstancePtr | ) |

Read RX I3C FIFO.

Parameters

  BaseAddress | contains the base address of the device.

Returns
  None.

Note
  None.

References XI3c_Config::BaseAddress, XI3c::Config, XI3c::RecvBufferPtr, XI3c::RecvByteCount, XI3C_RD_FIFO_OFFSET, and XI3c_ReadReg.

Referenced by XI3c_IbiRecvPolled(), XI3c_MasterInterruptHandler(), and XI3c_MasterRecvPolled().

s32 XI3c_SendTransferCmd | ( | XI3c * | InstancePtr,
|  | XI3c_Cmd * | Cmd,
|  | u8 | Data
| ) |  |

This function sends the command.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  Cmd | is a pointer to the XI3c_Cmd.
  Data | is the command value.

Returns
  - XST_SUCCESS if everything went well.
  - XST_FAILURE if any error.

Note
  None.

< Broadcast address

< Write operation

< SIze of the command is 8 bits

References XI3c::IsReady, XI3c::SendBufferPtr, XI3c::SendByteCount, XI3c_FillCmdFifo(), and XI3c_WriteTxFifo().

Referenced by I3cMasterDaaExample(), I3cMasterIntrExample(), I3cMasterPolledExample(), XI3C_BusInit(), and XI3c_DynaAddrAssign().

s32 XI3c_SetSClk | ( | XI3c * | InstancePtr,
|  | u32 | SclkHz,
|  | u8 | Mode
| ) |  |

Sets I3C Scl clock frequency.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  SclkHz | is Scl clock to be configured in Hz.
  Mode | is the mode of operation I2C/I3C.

Returns
  The return value is XST_SUCCESS if successful.

Note
  None.

References XI3c_Config::BaseAddress, XI3c::Config, XI3c_Config::InputClockHz, XI3c_GetRevisionNumber, XI3C_OD_SCL_HIGH_TIME_OFFSET, XI3C_OD_SCL_LOW_TIME_OFFSET, XI3C_SCL_HIGH_TIME_OFFSET, XI3C_SCL_LOW_TIME_OFFSET, XI3C_SDA_HOLD_TIME_OFFSET, XI3C_THD_START_OFFSET, XI3C_TSU_START_OFFSET, XI3C_TSU_STOP_OFFSET, and XI3c_WriteReg.

void XI3c_SetStatusHandler | ( | XI3c * | InstancePtr,
|  | XI3c_IntrHandler | FunctionPtr
| ) |  |

This function sets the status handler, which the driver calls when it encounters conditions that should be reported to the higher layer software.

The handler executes in an interrupt context, so the amount of processing should be minimized

Refer to the xi3c.h file for a list of events. The events are defined to start with XI3C_EVENT_*.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  FunctionPtr | is the pointer to the callback function.

Returns
  None.

Note

The handler is called within interrupt context, so it should finish its work quickly.

References XI3c::IsReady, and XI3c::StatusHandler.

Referenced by I3cMasterIntrExample(), and I3cSlaveIntrExample().

void XI3c_SlaveInterruptHandler | ( | XI3c * | InstancePtr | ) |

The interrupt handler for the slave mode.

It does the slave side protocol handling for the interrupt-driven transfers.

If the slave is receiving data then the data is read from the FIFO and the slave has to send data on master request data need to write to FIFO. If all the data has been transferred then a completion event is signalled to the upper layer by calling the callback handler.

Parameters

  InstancePtr | is a pointer to the XI3c instance.

Returns
  None.

Note
  None.

References XI3c_Config::BaseAddress, XI3c::Config, XI3c::DirectCCC, XI3c::Error, XI3c::StatusHandler, XI3C_INTR_RESP_NOT_EMPTY_MASK, XI3C_INTR_STATUS_OFFSET, XI3c_ReadReg, and XI3c_WriteReg.

Referenced by I3cSlaveIntrExample().

s32 XI3c_SlaveRecv | ( | XI3c * | InstancePtr,
|  | u8 * | MsgPtr
| ) |  |

This function initiates a interrupt mode receive in slave mode.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  MsgPtr | is the pointer to the recv buffer.

Returns
  - XST_SUCCESS if everything went well.
  - XST_NO_DATA if MsgPtr is NULL.

Note
  None.

References XI3c::RecvBufferPtr.

Referenced by I3cSlaveIntrExample().

s32 XI3c_SlaveRecvPolled | ( | XI3c * | InstancePtr,
|  | u8 * | MsgPtr
| ) |  |

This function initiates a polled mode receive in slave mode.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  MsgPtr | is the pointer to the send buffer.

Returns
  - XST_SUCCESS if everything went well.
  - XST_RECV_ERROR if any error.
  - XST_NO_DATA if MsgPtr is NULL.

Note
  None.

References XI3c::RecvBufferPtr.

Referenced by I3cSlavePolledExample().

s32 XI3c_SlaveSend | ( | XI3c * | InstancePtr,
|  | u8 * | MsgPtr,
|  | u16 | ByteCount
| ) |  |

This function initiates a interrupt mode send in slave mode.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  MsgPtr | is the pointer to the send buffer.
  ByteCount | is the number of bytes to be sent.

Returns
  - XST_SUCCESS if everything went well.
  - XST_NO_DATA if MsgPtr is NULL.
    - Error code if any error.

Note
  None.

References XI3c::Config, XI3c_Config::RwFifoDepth, XI3c::SendBufferPtr, XI3c::SendByteCount, XI3c_FillSlaveSendCount, XI3c_GetMRL, XI3c_WrFifoLevel, and XI3c_WriteTxFifo().

Referenced by I3cSlaveIntrExample().

s32 XI3c_SlaveSendPolled | ( | XI3c * | InstancePtr,
|  | u8 * | MsgPtr,
|  | u16 | ByteCount
| ) |  |

This function initiates a polled mode send in slave mode.

It sends data to the FIFO and the master to pick them up.

Parameters

  InstancePtr | is a pointer to the XI3c instance.
  MsgPtr | is the pointer to the send buffer.
  ByteCount | is the number of bytes to be sent.

Returns
  - XST_SUCCESS if everything went well.
  - XST_SEND_ERROR if any error.
  - XST_NO_DATA if MsgPtr is NULL.

Note
  Caller need to wait for response after calling this function.

References XI3c::Config, XI3c_Config::RwFifoDepth, XI3c::SendBufferPtr, XI3c::SendByteCount, XI3c_FillSlaveSendCount, XI3c_GetMRL, XI3c_WrFifoLevel, and XI3c_WriteTxFifo().

Referenced by I3cSlavePolledExample().

void XI3c_WriteTxFifo | ( | XI3c * | InstancePtr | ) |

Fill I3C Write Tx FIFO.

Parameters

  BaseAddress | contains the base address of the device.

Returns
  None.

Note
  None.

References XI3c_Config::BaseAddress, XI3c::Config, XI3c::SendBufferPtr, XI3c::SendByteCount, XI3C_WR_FIFO_OFFSET, and XI3c_WriteReg.

Referenced by XI3c_DynaAddrAssign(), XI3c_MasterInterruptHandler(), XI3c_MasterSend(), XI3c_MasterSendPolled(), XI3c_SendTransferCmd(), XI3c_SlaveSend(), and XI3c_SlaveSendPolled().

## Variable Documentation

XI3c_Config XI3c_ConfigTable[XPAR_XI3C_NUM_INSTANCES]

Initial value:
= {
{
(u16)XPAR_XI3C_0_DEVICE_ID,
(u32)XPAR_XI3C_0_BASEADDR,
(u32)XPAR_XI3C_0_I3C_CLK_FREQ_HZ,
(u32)XPAR_XI3C_0_RW_FIFO_DEPTH,
(u32)XPAR_XI3C_0_WRITE_FIFO_THRESHOLD,
(u32)XPAR_XI3C_0_DEVICE_COUNT,
(u32)XPAR_XI3C_0_IBI_CAPABLE,
(u32)XPAR_XI3C_0_HJ_CAPABLE
(u32)XPAR_XI3C_0_DEVICE_ROLE
},
{
(u16)XPAR_XI3C_1_DEVICE_ID,
(u32)XPAR_XI3C_1_BASEADDR,
(u32)XPAR_XI3C_1_I3C_CLK_FREQ_HZ,
(u32)XPAR_XI3C_1_RW_FIFO_DEPTH,
(u32)XPAR_XI3C_1_WRITE_FIFO_THRESHOLD,
(u32)XPAR_XI3C_1_DEVICE_COUNT,
(u32)XPAR_XI3C_1_IBI_CAPABLE,
(u32)XPAR_XI3C_1_HJ_CAPABLE
(u32)XPAR_XI3C_1_DEVICE_ROLE
}
}

This table contains configuration information for each I3C device in the system.

Configuration table.

Referenced by XI3c_LookupConfig().

XI3c_Config XI3c_ConfigTable[]

Configuration table.

Configuration table.

Referenced by XI3c_LookupConfig().