| dppsu Vitis Drivers API Documentation

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Functions | Variables
xdppsu_selftest.c File Reference

## Overview

This file contains a diagnostic self-test function for the XDpPsu driver.

It will check many of the DisplayPort TX's register values against the default reset values as a sanity-check that the core is ready to be used.

Note
  None.

    MODIFICATION HISTORY:

    Ver   Who  Date     Changes

    1.0   aad  01/17/17 Initial release.
    1.1   aad  10/04/17 Removed not applicable registers

## Functions
u32 | XDpPsu_SelfTest (XDpPsu *InstancePtr)
| This function runs a self-test on the XDpPsu driver/device. More...

## Variables
u32 | ResetValues [XDPPSU_NUM_RESET_VALUES][2]
| This table contains the default values for the DisplayPort TX core's general usage registers. More...
u32 | ResetValuesMsa [XDPPSU_NUM_MSA_RESET_VALUES][2]
| This table contains the default values for the DisplayPort TX core's main stream attribute (MSA) registers. More...

## Function Documentation

u32 XDpPsu_SelfTest | ( | XDpPsu * | InstancePtr | ) |

This function runs a self-test on the XDpPsu driver/device.

The sanity test checks whether or not all tested registers hold their default reset values.

Parameters

  InstancePtr | is a pointer to the XDpPsu instance.

Returns
  - XST_SUCCESS if the self-test passed - all tested registers hold their default reset values.
  - XST_FAILURE otherwise.

Note
  None.

References XDpPsu_Config::BaseAddr, XDpPsu::Config, ResetValues, ResetValuesMsa, and XDpPsu_ReadReg.

Referenced by DpPsu_SelfTestExample().

## Variable Documentation

u32 ResetValues[XDPPSU_NUM_RESET_VALUES][2]

This table contains the default values for the DisplayPort TX core's general usage registers.

Referenced by XDpPsu_SelfTest().

u32 ResetValuesMsa[XDPPSU_NUM_MSA_RESET_VALUES][2]

Initial value:
=
{
{XDPPSU_MAIN_STREAM_HTOTAL, 0},
{XDPPSU_MAIN_STREAM_VTOTAL, 0},
{XDPPSU_MAIN_STREAM_POLARITY, 0},
{XDPPSU_MAIN_STREAM_HSWIDTH, 0},
{XDPPSU_MAIN_STREAM_VSWIDTH, 0},
{XDPPSU_MAIN_STREAM_HRES, 0},
{XDPPSU_MAIN_STREAM_VRES, 0},
{XDPPSU_MAIN_STREAM_HSTART, 0},
{XDPPSU_MAIN_STREAM_VSTART, 0},
{XDPPSU_MAIN_STREAM_MISC0, 0},
{XDPPSU_MAIN_STREAM_MISC1, 0},
{XDPPSU_M_VID, 0},
{XDPPSU_TU_SIZE, 0x40},
{XDPPSU_N_VID, 0},
{XDPPSU_USER_PIXEL_WIDTH, 1},
{XDPPSU_USER_DATA_COUNT_PER_LANE, 0},
{XDPPSU_MIN_BYTES_PER_TU, 0},
{XDPPSU_FRAC_BYTES_PER_TU, 0},
{XDPPSU_INIT_WAIT, 0x20}
}
XDPPSU_MAIN_STREAM_HSTART
#define XDPPSU_MAIN_STREAM_HSTART
Number of clocks between the leading edge of the horizontal sync and the start of active data...
Definition: xdppsu_hw.h:186
XDPPSU_INIT_WAIT
#define XDPPSU_INIT_WAIT
Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data t...
Definition: xdppsu_hw.h:255
XDPPSU_MAIN_STREAM_MISC1
#define XDPPSU_MAIN_STREAM_MISC1
Miscellaneous stream attributes.
Definition: xdppsu_hw.h:205
XDPPSU_N_VID
#define XDPPSU_N_VID
N value for the video stream as computed by the source core in asynchronous clock mode...
Definition: xdppsu_hw.h:222
XDPPSU_M_VID
#define XDPPSU_M_VID
M value for the video stream as computed by the source core in asynchronous clock mode...
Definition: xdppsu_hw.h:208
XDPPSU_MIN_BYTES_PER_TU
#define XDPPSU_MIN_BYTES_PER_TU
The minimum number of bytes per transfer unit.
Definition: xdppsu_hw.h:245
XDPPSU_MAIN_STREAM_HTOTAL
#define XDPPSU_MAIN_STREAM_HTOTAL
Total number of clocks in the horizontal framing period.
Definition: xdppsu_hw.h:161
XDPPSU_MAIN_STREAM_VSTART
#define XDPPSU_MAIN_STREAM_VSTART
Number of lines between the leading edge of the vertical sync and the first line of active data...
Definition: xdppsu_hw.h:193
XDPPSU_MAIN_STREAM_VTOTAL
#define XDPPSU_MAIN_STREAM_VTOTAL
Total number of lines in the video frame.
Definition: xdppsu_hw.h:166
XDPPSU_USER_DATA_COUNT_PER_LANE
#define XDPPSU_USER_DATA_COUNT_PER_LANE
Used to translate the number of pixels per line to the native internal 16-bit datapath.
Definition: xdppsu_hw.h:236
XDPPSU_MAIN_STREAM_VRES
#define XDPPSU_MAIN_STREAM_VRES
Number of active lines (the vertical resolution).
Definition: xdppsu_hw.h:183
XDPPSU_MAIN_STREAM_HRES
#define XDPPSU_MAIN_STREAM_HRES
Number of active pixels per line (the horizontal resolution).
Definition: xdppsu_hw.h:178
XDPPSU_TU_SIZE
#define XDPPSU_TU_SIZE
Size of a transfer unit in the framing logic.
Definition: xdppsu_hw.h:219
XDPPSU_FRAC_BYTES_PER_TU
#define XDPPSU_FRAC_BYTES_PER_TU
The fractional component when calculated the XDPPSU_MIN_BYTES_PER_TU register value.
Definition: xdppsu_hw.h:248
XDPPSU_MAIN_STREAM_POLARITY
#define XDPPSU_MAIN_STREAM_POLARITY
Polarity for the video sync signals.
Definition: xdppsu_hw.h:169
XDPPSU_MAIN_STREAM_MISC0
#define XDPPSU_MAIN_STREAM_MISC0
Miscellaneous stream attributes.
Definition: xdppsu_hw.h:202
XDPPSU_USER_PIXEL_WIDTH
#define XDPPSU_USER_PIXEL_WIDTH
Selects the width of the user data input port.
Definition: xdppsu_hw.h:233
XDPPSU_MAIN_STREAM_VSWIDTH
#define XDPPSU_MAIN_STREAM_VSWIDTH
Width of the vertical sync pulse.
Definition: xdppsu_hw.h:175
XDPPSU_MAIN_STREAM_HSWIDTH
#define XDPPSU_MAIN_STREAM_HSWIDTH
Width of the horizontal sync pulse.
Definition: xdppsu_hw.h:172

This table contains the default values for the DisplayPort TX core's main stream attribute (MSA) registers.

Referenced by XDpPsu_SelfTest().