| mbox Vitis Drivers API Documentation

- Overview
- Data Structures
- APIs
- File List
- Examples

Macros
xmbox_hw.h File Reference

## Macros
#define | XMbox_ReadReg(BaseAddress, RegOffset) Xil_In32((BaseAddress) + (RegOffset))
| Read one of the mbox registers. More...
#define | XMbox_WriteReg(BaseAddress, RegOffset, ValueToWrite) Xil_Out32(((BaseAddress) + (RegOffset)), (ValueToWrite))
| Write a specified value to a register of a mbox. More...
#define | XMbox_WriteMBox(BaseAddress, ValueToWrite) XMbox_WriteReg (BaseAddress, XMB_WRITE_REG_OFFSET, ValueToWrite)
| Write the mbox write register. More...
#define | XMbox_ReadMBox(BaseAddress) XMbox_ReadReg (BaseAddress, XMB_READ_REG_OFFSET)
| Read the mbox read FIFO. More...
#define | XMbox_IsEmptyHw(BaseAddress) ((XMbox_ReadReg (BaseAddress, XMB_STATUS_REG_OFFSET) & XMB_STATUS_FIFO_EMPTY))
| Checks if the Read FIFO is Empty. More...
#define | XMbox_IsFullHw(BaseAddress) ((XMbox_ReadReg (BaseAddress, XMB_STATUS_REG_OFFSET) & XMB_STATUS_FIFO_FULL))
| Checks if there is room in the Write FIFO. More...
Register Offset Definitions
Register offsets within a mbox.
#define | XMB_WRITE_REG_OFFSET 0x00
| Mbox write register. More...
#define | XMB_READ_REG_OFFSET 0x08
| Mbox read register. More...
#define | XMB_STATUS_REG_OFFSET 0x10
| Mbox status reg. More...
#define | XMB_ERROR_REG_OFFSET 0x14
| Mbox Error reg. More...
#define | XMB_SIT_REG_OFFSET 0x18
| Mbox send interrupt threshold register. More...
#define | XMB_RIT_REG_OFFSET 0x1C
| Mbox receive interrupt threshold register. More...
#define | XMB_IS_REG_OFFSET 0x20
| Mbox interrupt status register. More...
#define | XMB_IE_REG_OFFSET 0x24
| Mbox interrupt enable register. More...
#define | XMB_IP_REG_OFFSET 0x28
| Mbox interrupt pending register. More...
#define | XMB_CTRL_REG_OFFSET 0x2C
| Mbox control register. More...
Status register bit definitions
These status bits are used to poll the FIFOs
#define | XMB_STATUS_FIFO_EMPTY 0x00000001
| Receive FIFO is Empty. More...
#define | XMB_STATUS_FIFO_FULL 0x00000002
| Send FIFO is Full. More...
#define | XMB_STATUS_STA 0x00000004
| Send FIFO Threshold Status. More...
#define | XMB_STATUS_RTA 0x00000008
| Receive FIFO Threshold Status. More...
Interrupt Registers(s) bits definitions.
The IS, IE, and IP registers all have the same bit definition.
#define | XMB_IX_STA 0x01
| Send Threshold Active, when the number of Send FIFO entries is less than and equal to Send Interrupt Threshold. More...
#define | XMB_IX_RTA 0x02
| Receive Threshold Active, when the number of Receive FIFO entries is greater than Receive Interrupt Threshold. More...
#define | XMB_IX_ERR 0x04
| Mailbox Error, when read on empty or write on full. More...
Error bits definition.
#define | XMB_ERROR_FIFO_EMPTY 0x00000001
| Receive FIFO is Empty. More...
#define | XMB_ERROR_FIFO_FULL 0x00000002
| Send FIFO is Full. More...
Control register bits definition.
#define | XMB_CTRL_RESET_SEND_FIFO 0x00000001
| Clear Send FIFO. More...
#define | XMB_CTRL_RESET_RECV_FIFO 0x00000002
| Clear Receive FIFO. More...