| v_hdmitx1 Vitis Drivers API Documentation

- Overview
- Data Structures
- APIs
- File List

Data Structures | Macros
xv_hdmitx1_frl.h File Reference

## Overview

This is the main header file for Xilinx HDMI TX core.

HDMI TX core is used for transmitting the incoming video and audio streams. It consists of

- Transmitter core
- AXI4-Stream to Video Bridge
- Video Timing Controller and
- High-bandwidth Digital Content Protection (HDCP) (Optional).

The HDMI TX uses three AXI interfaces for Video, Audio and Processor:

- AXI4-Stream interface for Video, can be single, dual or quad pixels per clock and supports 8 and 10 bits per component.
- AXI4-Stream interface for Audio, accepts multiple channels uncompressed and compressed audio data.
- AXI4-Lite interface for processor, controls the transmitter. Please do refer AXI Reference Guide (UG761) for more information on AXI interfaces.

Transmitter core performs following operations:

- Converts video data from the video clock domain into the link clock domain.
- TMDS (Transition Minimized Differential Signaling) encoding.
- Merges encoded video data and packet data into a single HDMI stream.
- Optional HDMI stream is encrypted by an external HDCP module.
- Over samples HDMI stream if stream bandwidth is too low for the transceiver to handle.
- Scrambles encrypted/HDMI stream if data rate is above 3.4 Gbps otherwise bypasses the Scrambler.

AXI Video Bridge converts the incoming video AXI-stream to native video.

Video Timing Controller (VTC) generates the native video timing.

Core Features

For a full description of HDMI TX features, please see the hardware specification.

Software Initialization & Configuration

The application needs to do following steps in order for preparing the HDMI TX core to be ready.

- Call XV_HdmiTx1_LookupConfig using a device ID to find the core configuration.
- Call XV_HdmiTx1_CfgInitialize to initialize the device and the driver instance associated with it.

Interrupts

This driver provides interrupt handlers

- XV_HdmiTx1_IntrHandler, for handling the interrupts from the HDMI TX core PIO and DDC peripheral respectively.

Application developer needs to register interrupt handler with the processor, within their examples. Whenever processor calls registered application's interrupt handler associated with interrupt id, application's interrupt handler needs to call appropriate peripheral interrupt handler reading peripheral's Status register.

This driver provides XV_HdmiTx1_SetCallback API to register functions with HDMI TX core instance.

Virtual Memory

This driver supports Virtual Memory. The RTOS is responsible for calculating the correct device base address in Virtual Memory space.

Threads

This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.

Asserts

Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that users leave asserts on during development.

Building the driver

The HDMI TX driver is composed of several source files. This allows the user to build and link only those parts of the driver that are necessary.

     MODIFICATION HISTORY:
    s
     Ver   Who    Date     Changes

     1.00  EB     22/05/18 Initial release.

## Data Structures
struct | XV_HdmiTx1_Frl
| This typedef contains audio stream specific data structure. More...

## Macros
#define | XV_HDMITX1_FRL_H_
| Prevent circular inclusions by using protection macros. More...

## Enumerations
HDMI TX FRL training state
enum | XV_HdmiTx1_FrlTrainingState
HDMI TX LTP Type
enum | XV_HdmiTx1_FrlLtpType

## HDMI TX FRL Active Mode
#define | XV_HdmiTx1_FrlIntrEnable(InstancePtr)
| This macro enables interrupt in the HDMI TX FRL peripheral. More...
#define | XV_HdmiTx1_FrlIntrDisable(InstancePtr)
| This macro disables interrupt in the HDMI TX FRL peripheral. More...
#define | XV_HdmiTx1_FrlRcEnable(InstancePtr)
| This macro enables repeat count in the packetizer (with RC compress) in the HDMI TX FRL peripheral. More...
#define | XV_HdmiTx1_FrlRcDisable(InstancePtr)
| This macro disables repeat count in the packetizer (with RC compress) in the HDMI TX FRL peripheral. More...
#define | XV_HdmiTx1_SetFrlLinkClock(InstancePtr, Value)
| This macro sets the link clock of TX Core's FRL peripheral. More...
#define | XV_HdmiTx1_SetFrlVidClock(InstancePtr, Value)
| This macro sets the video clock of TX Core's FRL peripheral. More...
#define | XV_HdmiTx1_FrlRateLockEnable(InstancePtr) (InstancePtr)->Stream.Frl.RateLock = TRUE
| This macro enables FRL Rate Lock. More...
#define | XV_HdmiTx1_FrlRateLockDisable(InstancePtr) (InstancePtr)->Stream.Frl.RateLock = FALSE
| This macro disables FRL Rate Lock. More...
enum | XV_HdmiTx1_FrlActiveMode

## Macro Definition Documentation

#define XV_HDMITX1_FRL_H_

Prevent circular inclusions by using protection macros.

#define XV_HdmiTx1_FrlIntrDisable | ( |  | InstancePtr | ) |

Value:
XV_HdmiTx1_WriteReg((InstancePtr)->Config.BaseAddress, \
(XV_HDMITX1_FRL_CTRL_CLR_OFFSET), \
(XV_HDMITX1_FRL_CTRL_IE_MASK))
XV_HdmiTx1_WriteReg
#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI TX register.
Definition: xv_hdmitx1_hw.h:763
XV_HDMITX1_FRL_CTRL_CLR_OFFSET
#define XV_HDMITX1_FRL_CTRL_CLR_OFFSET
FRL Control Register Clear offset.
Definition: xv_hdmitx1_hw.h:571
XV_HDMITX1_FRL_CTRL_IE_MASK
#define XV_HDMITX1_FRL_CTRL_IE_MASK
FRL Control Interrupt Enable mask.
Definition: xv_hdmitx1_hw.h:600

This macro disables interrupt in the HDMI TX FRL peripheral.

Parameters

  InstancePtr | is a pointer to the XV_HdmiTx1 core instance.

Returns
  None.

Note
  C-style signature: void XV_HdmiTx1_FrlIntrDisable(XV_HdmiTx1 *InstancePtr)

Referenced by XV_HdmiTx1_CfgInitialize().

#define XV_HdmiTx1_FrlIntrEnable | ( |  | InstancePtr | ) |

Value:
XV_HdmiTx1_WriteReg((InstancePtr)->Config.BaseAddress, \
(XV_HDMITX1_FRL_CTRL_SET_OFFSET), \
(XV_HDMITX1_FRL_CTRL_IE_MASK))
XV_HdmiTx1_WriteReg
#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI TX register.
Definition: xv_hdmitx1_hw.h:763
XV_HDMITX1_FRL_CTRL_IE_MASK
#define XV_HDMITX1_FRL_CTRL_IE_MASK
FRL Control Interrupt Enable mask.
Definition: xv_hdmitx1_hw.h:600
XV_HDMITX1_FRL_CTRL_SET_OFFSET
#define XV_HDMITX1_FRL_CTRL_SET_OFFSET
FRL Control Register Set offset.
Definition: xv_hdmitx1_hw.h:568

This macro enables interrupt in the HDMI TX FRL peripheral.

Parameters

  InstancePtr | is a pointer to the XV_HdmiTx1 core instance.

Returns
  None.

Note
  C-style signature: void XV_HdmiTx1_FrlIntrEnable(XV_HdmiTx1 *InstancePtr)

Referenced by XV_HdmiTx1_CfgInitialize().

#define XV_HdmiTx1_FrlRateLockDisable | ( |  | InstancePtr | ) | (InstancePtr)->Stream.Frl.RateLock = FALSE

This macro disables FRL Rate Lock.

With FRL Rate Lock disabled, TX core will behave according to the HDMI spec and will drop FRL Rate when the sink requests to drop FRL rate.

Parameters

  InstancePtr | is a pointer to the XV_HdmiTx1 core instance.

Returns
  None.

Note
  C-style signature: void XV_HdmiTx1_FrlRateLockDisable(XV_HdmiTx1 *InstancePtr)

#define XV_HdmiTx1_FrlRateLockEnable | ( |  | InstancePtr | ) | (InstancePtr)->Stream.Frl.RateLock = TRUE

This macro enables FRL Rate Lock.

With FRL Rate Lock enabled, TX core will not change to any other FRL Rate even when it is requested by the sink to drop FRL rate.

Parameters

  InstancePtr | is a pointer to the XV_HdmiTx1 core instance.

Returns
  None.

Note
  C-style signature: void XV_HdmiTx1_FrlRateLockEnable(XV_HdmiTx1 *InstancePtr)

#define XV_HdmiTx1_FrlRcDisable | ( |  | InstancePtr | ) |

Value:
XV_HdmiTx1_WriteReg((InstancePtr)->Config.BaseAddress, \
(XV_HDMITX1_FRL_CTRL_SET_OFFSET), \
(XV_HDMITX1_FRL_CTRL_TST_RC_MASK))
XV_HdmiTx1_WriteReg
#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI TX register.
Definition: xv_hdmitx1_hw.h:763
XV_HDMITX1_FRL_CTRL_TST_RC_MASK
#define XV_HDMITX1_FRL_CTRL_TST_RC_MASK
FRL RC Compress mask.
Definition: xv_hdmitx1_hw.h:612
XV_HDMITX1_FRL_CTRL_SET_OFFSET
#define XV_HDMITX1_FRL_CTRL_SET_OFFSET
FRL Control Register Set offset.
Definition: xv_hdmitx1_hw.h:568

This macro disables repeat count in the packetizer (with RC compress) in the HDMI TX FRL peripheral.

Parameters

  InstancePtr | is a pointer to the XV_HdmiTx1 core instance.

Returns
  None.

Note
  C-style signature: void XV_HdmiTx1_FrlRcDisable(XV_HdmiTx1 *InstancePtr)

#define XV_HdmiTx1_FrlRcEnable | ( |  | InstancePtr | ) |

Value:
XV_HdmiTx1_WriteReg((InstancePtr)->Config.BaseAddress, \
(XV_HDMITX1_FRL_CTRL_CLR_OFFSET), \
(XV_HDMITX1_FRL_CTRL_TST_RC_MASK))
XV_HdmiTx1_WriteReg
#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI TX register.
Definition: xv_hdmitx1_hw.h:763
XV_HDMITX1_FRL_CTRL_CLR_OFFSET
#define XV_HDMITX1_FRL_CTRL_CLR_OFFSET
FRL Control Register Clear offset.
Definition: xv_hdmitx1_hw.h:571
XV_HDMITX1_FRL_CTRL_TST_RC_MASK
#define XV_HDMITX1_FRL_CTRL_TST_RC_MASK
FRL RC Compress mask.
Definition: xv_hdmitx1_hw.h:612

This macro enables repeat count in the packetizer (with RC compress) in the HDMI TX FRL peripheral.

Parameters

  InstancePtr | is a pointer to the XV_HdmiTx1 core instance.

Returns
  None.

Note
  C-style signature: void XV_HdmiTx1_FrlRcEnable(XV_HdmiTx1 *InstancePtr)

#define XV_HdmiTx1_SetFrlLinkClock | ( |  | InstancePtr,
|  |  | Value
| ) |  |

Value:
{ \
XV_HdmiTx1_WriteReg((InstancePtr)->Config.BaseAddress, \
(XV_HDMITX1_FRL_LNK_CLK_OFFSET), \
(Value)); \
}
XV_HdmiTx1_WriteReg
#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI TX register.
Definition: xv_hdmitx1_hw.h:763
XV_HDMITX1_FRL_LNK_CLK_OFFSET
#define XV_HDMITX1_FRL_LNK_CLK_OFFSET
FRL Link Clock Register offset.
Definition: xv_hdmitx1_hw.h:580

This macro sets the link clock of TX Core's FRL peripheral.

Parameters

  InstancePtr | is a pointer to the XHdmi_Tx core instance.
  Value | specifies the Link Clock

Returns
  None.

Note
  C-style signature: void XV_HdmiTx1_SetFrlLinkClock(XV_HdmiTx1 *InstancePtr, u16 Value)

#define XV_HdmiTx1_SetFrlVidClock | ( |  | InstancePtr,
|  |  | Value
| ) |  |

Value:
{ \
XV_HdmiTx1_WriteReg((InstancePtr)->Config.BaseAddress, \
(XV_HDMITX1_FRL_VID_CLK_OFFSET), \
(Value)); \
}
XV_HdmiTx1_WriteReg
#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI TX register.
Definition: xv_hdmitx1_hw.h:763
XV_HDMITX1_FRL_VID_CLK_OFFSET
#define XV_HDMITX1_FRL_VID_CLK_OFFSET
FRL Video Clock Register offset.
Definition: xv_hdmitx1_hw.h:583

This macro sets the video clock of TX Core's FRL peripheral.

Parameters

  InstancePtr | is a pointer to the XHdmi_Tx core instance.
  Value | specifies the Video Clock

Returns
  None.

Note
  C-style signature: void XV_HdmiTx1_SetFrlVidClock(XV_HdmiTx1 *InstancePtr, u16 Value)