| v_frmbuf_wr Vitis Drivers API Documentation

- Overview
- Data Structures
- APIs
- File List

v_frmbuf_wr Documentation

This header file contains layer 2 API's of the frame buffer write core driver.The functions contained herein provides a high level implementation of features provided by the IP, abstracting away the register level details from the user

Frame Buffer Write IP Features

The Frame Buffer Write IP supports following features

- AXI4-Stream Input
- 1, 2, or 4 pixel-wide video interface
- 8/10 bits per component
- Up to 16 different memory color formats (user configurable)

Dependency

This driver makes use of the video enumerations and data types defined in the Xilinx Video Common Driver (video_common_vX.x) and as such the common driver must be included as dependency to compile this driver

Initialization & Configuration

The device driver enables higher layer software (e.g., an application) to communicate with the frame buffer write core.

Driver is built with layered architecture

- Layer 1 provides API's to peek/poke registers at HW level.
- Layer 2 provides API's that abstract sub-core functionality, providing an easy to use feature interface

Before using the layer-2 API's user must initialize the core by calling API XVFrmbufWr_Initialize(). This function will look for a configuration structure for the device and initialize it to defined HW settings. It is recommended user always make use of Layer-2 API to interact with this core. Advanced users always have the capability to directly interact with the IP core using Layer-1 API's that perform low level register peek/poke.

Pre-Requisite's

- Application must set the memory address using provided API Address must be aligned to memory width. This can be computed with following equation Align = 2 * PPC * 4 Bytes (where PPC is the Pixels/Clock selected in IP configuration)
- The Stride must be provided in Bytes and must be aligned to memory width. This can be computed with following equation StrideInBytes = 2 * PPC * 4 Bytes (where PPC is the Pixels/Clock selected in IP configuration)

Interrupts

Driver is configured to operate both in polling as well as interrupt mode.

- To use interrupt based processing, application must set up the system's interrupt controller and connect the XVFrmbufWr_InterruptHandler function to service interrupts. Next interrupts must be enabled using the provided API. When an interrupt occurs, ISR will confirm if frame processing is is done/ready. If call back is registered such function will be called and application can apply new setting updates here. Subsequently next frame processing will be triggered with new settings.
- To use polling method disable interrupts using the provided API. Doing so will configure the IP to keep processing frames without sw intervention.
- Polling mode is the default configuration set during driver initialization

Virtual Memory

This driver supports Virtual Memory. The RTOS is responsible for calculating the correct device base address in Virtual Memory space.

Threads

This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.

    MODIFICATION HISTORY:

    Ver   Who    Date     Changes

    1.00  vyc   04/05/17   Initial Release
    2.00  vyc   10/04/17   Add second buffer pointer for semi-planar formats
                           Add new memory formats BGRX8 and UYVY8
    3.00  vyc   04/04/18   Add interlaced support
                           Add new memory format BGR8
                           Add interrupt handler for ap_ready
    4.10  vv    02/05/19   Added new pixel formats with 12 and 16 bpc.
    4.50  kp    12/07/21   Added new 3 planar video format Y_U_V8.
    4.60  kp    10/27/21   Added new 3 planar video format Y_U_V10.
    4.70  pg    05/23/23   Added new 3 planar video format Y_U_V8_420.