11#ifndef TRC_HARDWARE_PORT_H
12#define TRC_HARDWARE_PORT_H
14#include <trcDefines.h>
21#define TRACE_ALLOC_CRITICAL_SECTION_NAME xTraceCriticalSectionStatus
23#if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_NOT_SET)
24 #error "TRC_CFG_HARDWARE_PORT not selected - see trcConfig.h"
96#if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_NOT_SET)
97 #error "TRC_CFG_HARDWARE_PORT not selected - see trcConfig.h"
100#if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Win32)
102void vTraceTimerReset(
void);
103uint32_t uiTraceTimerGetFrequency(
void);
104uint32_t uiTraceTimerGetValue(
void);
106#define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
107#define TRC_HWTC_COUNT ((TraceUnsignedBaseType_t)uiTraceTimerGetValue())
108#define TRC_HWTC_PERIOD 0
109#define TRC_HWTC_DIVISOR 1
110#define TRC_HWTC_FREQ_HZ ((TraceUnsignedBaseType_t)uiTraceTimerGetFrequency())
112#define TRC_IRQ_PRIORITY_ORDER 1
114#define TRC_PORT_SPECIFIC_INIT() vTraceTimerReset()
116#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Win64)
118void vTraceTimerReset(
void);
119uint32_t uiTraceTimerGetFrequency(
void);
120uint32_t uiTraceTimerGetValue(
void);
122#define TRC_BASE_TYPE int64_t
124#define TRC_UNSIGNED_BASE_TYPE uint64_t
126#define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
127#define TRC_HWTC_COUNT ((TraceUnsignedBaseType_t)uiTraceTimerGetValue())
128#define TRC_HWTC_PERIOD 0
129#define TRC_HWTC_DIVISOR 1
130#define TRC_HWTC_FREQ_HZ ((TraceUnsignedBaseType_t)uiTraceTimerGetFrequency())
132#define TRC_IRQ_PRIORITY_ORDER 1
134#define TRC_PORT_SPECIFIC_INIT() vTraceTimerReset()
136#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_HWIndependent)
138 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
139 #define TRC_HWTC_COUNT 0
140 #define TRC_HWTC_PERIOD 1
141 #define TRC_HWTC_DIVISOR 1
142 #define TRC_HWTC_FREQ_HZ TRC_TICK_RATE_HZ
145 #define TRC_IRQ_PRIORITY_ORDER NOT_SET
147#elif ((TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_Cortex_M) || (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_Cortex_M_NRF_SD))
150 #error "Can't find the CMSIS API. Please include your processor's header file in trcConfig.h"
153#if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_Cortex_M)
154 #define TRACE_ALLOC_CRITICAL_SECTION() TraceUnsignedBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME;
155 #define TRACE_ENTER_CRITICAL_SECTION() {TRACE_ALLOC_CRITICAL_SECTION_NAME = __get_PRIMASK(); __set_PRIMASK(1);}
156 #define TRACE_EXIT_CRITICAL_SECTION() {__set_PRIMASK(TRACE_ALLOC_CRITICAL_SECTION_NAME);}
158 #include "nrf_nvic.h"
159 #define TRACE_ALLOC_CRITICAL_SECTION() TraceUnsignedBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME;
160 #define TRACE_ENTER_CRITICAL_SECTION() {(void) sd_nvic_critical_region_enter((uint8_t*)&TRACE_ALLOC_CRITICAL_SECTION_NAME);}
161 #define TRACE_EXIT_CRITICAL_SECTION() {(void) sd_nvic_critical_region_exit((uint8_t)TRACE_ALLOC_CRITICAL_SECTION_NAME);}
174 #if ((__CORTEX_M >= 0x03) && (! defined TRC_CFG_ARM_CM_USE_SYSTICK))
176 void xTraceHardwarePortInitCortexM(
void);
178 #define TRC_REG_DEMCR (*(volatile uint32_t*)0xE000EDFC)
179 #define TRC_REG_DWT_CTRL (*(volatile uint32_t*)0xE0001000)
180 #define TRC_REG_DWT_CYCCNT (*(volatile uint32_t*)0xE0001004)
181 #define TRC_REG_DWT_EXCCNT (*(volatile uint32_t*)0xE000100C)
183 #define TRC_REG_ITM_LOCKACCESS (*(volatile uint32_t*)0xE0001FB0)
184 #define TRC_ITM_LOCKACCESS_UNLOCK (0xC5ACCE55)
187 #define TRC_DEMCR_TRCENA (1 << 24)
190 #define TRC_DWT_CTRL_NOPRFCNT (1 << 24)
193 #define TRC_DWT_CTRL_NOCYCCNT (1 << 25)
196 #define TRC_DWT_CTRL_EXCEVTENA (1 << 18)
199 #define TRC_DWT_CTRL_CYCCNTENA (1)
201 #define TRC_PORT_SPECIFIC_INIT() xTraceHardwarePortInitCortexM()
203 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
204 #define TRC_HWTC_COUNT TRC_REG_DWT_CYCCNT
205 #define TRC_HWTC_PERIOD 0
206 #define TRC_HWTC_DIVISOR 4
207 #define TRC_HWTC_FREQ_HZ TRACE_CPU_CLOCK_HZ
208 #define TRC_IRQ_PRIORITY_ORDER 0
212 #ifdef _CMSIS_RP2040_H_
213 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
214 #define TRC_HWTC_COUNT (*((volatile uint32_t*)0x4005400c))
215 #define TRC_HWTC_PERIOD 0
216 #define TRC_HWTC_DIVISOR 1
217 #define TRC_HWTC_FREQ_HZ 1000000
218 #define TRC_IRQ_PRIORITY_ORDER 0
220 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
221 #define TRC_HWTC_COUNT (*((volatile uint32_t*)0xE000E018))
222 #define TRC_HWTC_PERIOD ((*((volatile uint32_t*)0xE000E014)) + 1)
223 #define TRC_HWTC_DIVISOR 4
224 #define TRC_HWTC_FREQ_HZ TRACE_CPU_CLOCK_HZ
225 #define TRC_IRQ_PRIORITY_ORDER 0
230#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Renesas_RX600)
231 #define TRACE_ALLOC_CRITICAL_SECTION() TraceBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME;
232 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = TRC_KERNEL_PORT_SET_INTERRUPT_MASK(); }
233 #define TRACE_EXIT_CRITICAL_SECTION() { TRC_KERNEL_PORT_CLEAR_INTERRUPT_MASK(TRACE_ALLOC_CRITICAL_SECTION_NAME); }
235 #include <iodefine.h>
237 #if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING)
239 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
240 #define TRC_HWTC_COUNT (CMT0.CMCNT)
242 #elif (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT)
245 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
246 #define TRC_HWTC_COUNT (CMT0.CMCOR - CMT0.CMCNT)
250 #define TRC_HWTC_PERIOD (CMT0.CMCOR + 1)
251 #define TRC_HWTC_DIVISOR 1
252 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
253 #define TRC_IRQ_PRIORITY_ORDER 1
255#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_MICROCHIP_PIC24_PIC32)
257 #define TRACE_ALLOC_CRITICAL_SECTION() TraceBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME;
258 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = TRC_KERNEL_PORT_SET_INTERRUPT_MASK(); }
259 #define TRACE_EXIT_CRITICAL_SECTION() { TRC_KERNEL_PORT_CLEAR_INTERRUPT_MASK(TRACE_ALLOC_CRITICAL_SECTION_NAME); }
261 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
262 #define TRC_HWTC_COUNT (TMR1)
263 #define TRC_HWTC_PERIOD (PR1 + 1)
264 #define TRC_HWTC_DIVISOR 1
265 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
266 #define TRC_IRQ_PRIORITY_ORDER 1
268#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_TEXAS_INSTRUMENTS_TMS570_RM48)
270 #define TRC_RTIFRC0 *((uint32_t *)0xFFFFFC10)
271 #define TRC_RTICOMP0 *((uint32_t *)0xFFFFFC50)
272 #define TRC_RTIUDCP0 *((uint32_t *)0xFFFFFC54)
274 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
275 #define TRC_HWTC_COUNT (TRC_RTIFRC0 - (TRC_RTICOMP0 - TRC_RTIUDCP0))
276 #define TRC_HWTC_PERIOD (TRC_RTIUDCP0)
277 #define TRC_HWTC_DIVISOR 1
278 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
279 #define TRC_IRQ_PRIORITY_ORDER 0
281#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Atmel_AT91SAM7)
285 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
286 #define TRC_HWTC_COUNT ((uint32_t)(AT91C_BASE_PITC->PITC_PIIR & 0xFFFFF))
287 #define TRC_HWTC_PERIOD ((uint32_t)(AT91C_BASE_PITC->PITC_PIMR + 1))
288 #define TRC_HWTC_DIVISOR 1
289 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
290 #define TRC_IRQ_PRIORITY_ORDER 1
292#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Atmel_UC3A0)
298 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
299 #define TRC_HWTC_COUNT ((uint32_t)sysreg_read(AVR32_COUNT))
300 #define TRC_HWTC_PERIOD ((uint32_t)(sysreg_read(AVR32_COMPARE) + 1))
301 #define TRC_HWTC_DIVISOR 1
302 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
303 #define TRC_IRQ_PRIORITY_ORDER 1
305#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_NXP_LPC210X)
311 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
312 #define TRC_HWTC_COUNT *((uint32_t *)0xE0004008 )
313 #define TRC_HWTC_PERIOD *((uint32_t *)0xE0004018 )
314 #define TRC_HWTC_DIVISOR 1
315 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
316 #define TRC_IRQ_PRIORITY_ORDER 0
318#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_TEXAS_INSTRUMENTS_MSP430)
322 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
323 #define TRC_HWTC_COUNT (TA0R)
324 #define TRC_HWTC_PERIOD (((uint16_t)TACCR0)+1)
325 #define TRC_HWTC_DIVISOR 1
326 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
327 #define TRC_IRQ_PRIORITY_ORDER 1
329#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_PPC405)
333 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
334 #define TRC_HWTC_COUNT mfspr(0x3db)
335 #define TRC_HWTC_PERIOD (TRACE_CPU_CLOCK_HZ / TRC_TICK_RATE_HZ)
336 #define TRC_HWTC_DIVISOR 1
337 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
338 #define TRC_IRQ_PRIORITY_ORDER 0
340#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_PPC440)
346 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
347 #define TRC_HWTC_COUNT mfspr(0x016)
348 #define TRC_HWTC_PERIOD (TRACE_CPU_CLOCK_HZ / TRC_TICK_RATE_HZ)
349 #define TRC_HWTC_DIVISOR 1
350 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
351 #define TRC_IRQ_PRIORITY_ORDER 0
353#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_MICROBLAZE)
361 #include <xtmrctr_l.h>
363 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
364 #define TRC_HWTC_COUNT XTmrCtr_GetTimerCounterReg( XPAR_TMRCTR_0_BASEADDR, 0 )
365 #define TRC_HWTC_PERIOD (XTmrCtr_GetLoadReg( XPAR_TMRCTR_0_BASEADDR, 0) + 1)
366 #define TRC_HWTC_DIVISOR 16
367 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
368 #define TRC_IRQ_PRIORITY_ORDER 0
370#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_ZyncUltraScaleR5)
372 extern TraceUnsignedBaseType_t cortex_a9_r5_enter_critical(
void);
373 extern void cortex_a9_r5_exit_critical(TraceUnsignedBaseType_t irq_already_masked_at_enter);
375 #define TRACE_ALLOC_CRITICAL_SECTION() TraceUnsignedBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME;
377 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = cortex_a9_r5_enter_critical(); }
379 #define TRACE_EXIT_CRITICAL_SECTION() { cortex_a9_r5_exit_critical(TRACE_ALLOC_CRITICAL_SECTION_NAME); }
381 #include <xttcps_hw.h>
383 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
384 #define TRC_HWTC_COUNT (*(volatile uint32_t *)(configTIMER_BASEADDR + XTTCPS_COUNT_VALUE_OFFSET))
385 #define TRC_HWTC_PERIOD (*(volatile uint32_t *)(configTIMER_BASEADDR + XTTCPS_INTERVAL_VAL_OFFSET))
386 #define TRC_HWTC_DIVISOR 16
387 #define TRC_HWTC_FREQ_HZ (TRC_HWTC_PERIOD * TRC_TICK_RATE_HZ)
388 #define TRC_IRQ_PRIORITY_ORDER 0
392 static inline uint32_t prvGetCPSR(
void)
396 asm volatile (
" mrs %0, cpsr" :
"=r" (ret) : );
400 #error "Only GCC Supported!"
403#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Altera_NiosII)
408 #include <altera_avalon_timer_regs.h>
409 #include <sys/alt_irq.h>
411 #define TRACE_ALLOC_CRITICAL_SECTION() alt_irq_context TRACE_ALLOC_CRITICAL_SECTION_NAME;
412 #define TRACE_ENTER_CRITICAL_SECTION(){TRACE_ALLOC_CRITICAL_SECTION_NAME = alt_irq_disable_all();}
413 #define TRACE_EXIT_CRITICAL_SECTION() {alt_irq_enable_all(TRACE_ALLOC_CRITICAL_SECTION_NAME);}
421 #define SYSTEM_TIMER_BASE NOT_SET
423 #if (SYSTEM_TIMER == NOT_SET)
424 #error "Set SYSTEM_TIMER_BASE to the timer base used for system ticks."
427 static inline uint32_t altera_nios2_GetTimerSnapReg(
void)
432 IOWR_ALTERA_AVALON_TIMER_SNAPL(SYSTEM_TIMER_BASE, 0);
433 return (IORD_ALTERA_AVALON_TIMER_SNAPH(SYSTEM_TIMER_BASE) << 16) | IORD_ALTERA_AVALON_TIMER_SNAPL(SYSTEM_TIMER_BASE);
436 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
437 #define TRC_HWTC_COUNT altera_nios2_GetTimerSnapReg()
438 #define TRC_HWTC_PERIOD (configCPU_CLOCK_HZ / configTICK_RATE_HZ )
439 #define TRC_HWTC_DIVISOR 16
440 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
441 #define TRC_IRQ_PRIORITY_ORDER 0
443#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_CORTEX_A9)
461 extern TraceUnsignedBaseType_t cortex_a9_r5_enter_critical(
void);
462 extern void cortex_a9_r5_exit_critical(TraceUnsignedBaseType_t irq_already_masked_at_enter);
464 #define TRACE_ALLOC_CRITICAL_SECTION() TraceUnsignedBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME;
465 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = cortex_a9_r5_enter_critical(); }
466 #define TRACE_EXIT_CRITICAL_SECTION() { cortex_a9_r5_exit_critical(TRACE_ALLOC_CRITICAL_SECTION_NAME); }
469 #define TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS 0
471 #if (TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS == 0)
472 #error "Please specify TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS."
475 #define TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET 0x0600
476 #define TRC_CA9_MPCORE_PRIVCTR_PERIOD_REG (*(volatile uint32_t*)(TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x00))
477 #define TRC_CA9_MPCORE_PRIVCTR_COUNTER_REG (*(volatile uint32_t*)(TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x04))
478 #define TRC_CA9_MPCORE_PRIVCTR_CONTROL_REG (*(volatile uint32_t*)(TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x08))
480 #define TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK 0x0000FF00
481 #define TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT 8
482 #define TRC_CA9_MPCORE_PRIVCTR_PRESCALER (((TRC_CA9_MPCORE_PRIVCTR_CONTROL_REG & TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK) >> TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT) + 1)
484 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
485 #define TRC_HWTC_COUNT TRC_CA9_MPCORE_PRIVCTR_COUNTER_REG
486 #define TRC_HWTC_PERIOD (TRC_CA9_MPCORE_PRIVCTR_PERIOD_REG + 1)
494 #define TRC_HWTC_DIVISOR 1
496 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
497 #define TRC_IRQ_PRIORITY_ORDER 0
501 static inline uint32_t prvGetCPSR(
void)
505 asm volatile (
" mrs %0, cpsr" :
"=r" (ret) : );
509 #error "Only GCC Supported!"
512#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_CYCLONE_V_HPS)
513 #include "alt_clock_manager.h"
515 extern TraceUnsignedBaseType_t cortex_a9_r5_enter_critical(
void);
516 extern void cortex_a9_r5_exit_critical(TraceUnsignedBaseType_t irq_already_masked_at_enter);
518 #define TRACE_ALLOC_CRITICAL_SECTION() TraceUnsignedBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME;
519 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = cortex_a9_r5_enter_critical(); }
520 #define TRACE_EXIT_CRITICAL_SECTION() { cortex_a9_r5_exit_critical(TRACE_ALLOC_CRITICAL_SECTION_NAME); }
522 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
523 #define TRC_HWTC_COUNT *((uint32_t *)0xFFFEC200)
524 #define TRC_HWTC_PERIOD 0
525 #define TRC_HWTC_DIVISOR 1
526 #define TRC_HWTC_FREQ_HZ (({ \
528 alt_clk_freq_get( ALT_CLK_MPU_PERIPH, &__freq ); \
531 #define TRC_IRQ_PRIORITY_ORDER 0
535 static inline uint32_t prvGetCPSR(
void)
539 __asm__ __volatile__(
" mrs %0, cpsr" :
"=r" (ret) : );
543 #error "Only GCC Supported!"
546#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ZEPHYR)
548 #define TRC_BASE_TYPE int64_t
549 #define TRC_UNSIGNED_BASE_TYPE uint64_t
551 #define TRC_BASE_TYPE int32_t
552 #define TRC_UNSIGNED_BASE_TYPE uint32_t
555 #define TRACE_ALLOC_CRITICAL_SECTION() TraceBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME;
556 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = irq_lock(); }
557 #define TRACE_EXIT_CRITICAL_SECTION() { irq_unlock(TRACE_ALLOC_CRITICAL_SECTION_NAME); }
559 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
560 #define TRC_HWTC_COUNT k_cycle_get_32()
561 #define TRC_HWTC_PERIOD (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
562 #define TRC_HWTC_DIVISOR 4
563 #define TRC_HWTC_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
564 #define TRC_IRQ_PRIORITY_ORDER 0
566 #define TRC_PORT_SPECIFIC_INIT()
568#elif ((TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XTensa_LX6) || (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XTensa_LX7))
573 #if CONFIG_FREERTOS_UNICORE == 1
575 #define TRACE_ALLOC_CRITICAL_SECTION() TraceUnsignedBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME;
576 #define TRACE_ENTER_CRITICAL_SECTION() {TRACE_ALLOC_CRITICAL_SECTION_NAME = __extension__({ unsigned __tmp; \
577 __asm__ __volatile__("rsil %0, 15\n" \
578 : "=a" (__tmp) : : "memory" ); \
580 #define TRACE_EXIT_CRITICAL_SECTION() {portCLEAR_INTERRUPT_MASK_FROM_ISR(TRACE_ALLOC_CRITICAL_SECTION_NAME);}
582 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
583 #define TRC_HWTC_COUNT ({ unsigned int __ccount; \
584 __asm__ __volatile__("rsr.ccount %0" : "=a"(__ccount)); \
586#ifdef CONFIG_IDF_TARGET_ESP32
587 #define TRC_HWTC_FREQ_HZ (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ * 1000000)
588#elif defined(CONFIG_IDF_TARGET_ESP32S2)
589 #define TRC_HWTC_FREQ_HZ (CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ * 1000000)
591 #error "Invalid IDF target, check your sdkconfig."
593 #define TRC_HWTC_PERIOD 0
594 #define TRC_HWTC_DIVISOR 4
595 #define TRC_IRQ_PRIORITY_ORDER 0
603 uint32_t prvGetSMPTimestamp();
605 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
606 #define TRC_HWTC_COUNT prvGetSMPTimestamp()
607 #define TRC_HWTC_FREQ_HZ 40000000
608 #define TRC_HWTC_PERIOD 0
609 #define TRC_HWTC_DIVISOR 4
610 #define TRC_IRQ_PRIORITY_ORDER 0
613 #if !defined(TRC_HWTC_FREQ_HZ)
614 #error "The XTensa LX6/LX7 trace hardware clock frequency is not defined."
617#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_RISCV_RV32I)
618 #define TRACE_ALLOC_CRITICAL_SECTION() TraceUnsignedBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME;
619 #define TRACE_ENTER_CRITICAL_SECTION() __asm__ __volatile__("csrr %0, mstatus \n\t" \
620 "csrci mstatus, 8 \n\t" \
621 "andi %0, %0, 8 \n\t" \
622 : "=r"(TRACE_ALLOC_CRITICAL_SECTION_NAME))
623 #define TRACE_EXIT_CRITICAL_SECTION() __asm__ __volatile__("csrr a1, mstatus \n\t" \
624 "or %0, %0, a1 \n\t" \
625 "csrs mstatus, %0 \n\t" \
627 : "r" (TRACE_ALLOC_CRITICAL_SECTION_NAME) \
629 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
630 #define TRC_HWTC_COUNT ({ unsigned int __count; \
631 __asm__ __volatile__("rdcycle %0" : "=r"(__count)); \
633 #define TRC_HWTC_PERIOD 0
634 #define TRC_HWTC_DIVISOR 1
635 #define TRC_HWTC_FREQ_HZ 16000000
636 #define TRC_IRQ_PRIORITY_ORDER 0
638#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XMOS_XCOREAI)
639 #define TRC_PORT_SPECIFIC_INIT()
640 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
641 #define TRC_HWTC_COUNT xscope_gettime()
642 #define TRC_HWTC_PERIOD (configCPU_CLOCK_HZ / configTICK_RATE_HZ )
643 #define TRC_HWTC_DIVISOR 4
644 #define TRC_HWTC_FREQ_HZ 100000000
645 #define TRC_IRQ_PRIORITY_ORDER 0
647#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_POWERPC_Z4)
651 #define TRACE_ALLOC_CRITICAL_SECTION() TraceBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME;
652 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = TRC_KERNEL_PORT_SET_INTERRUPT_MASK(); }
653 #define TRACE_EXIT_CRITICAL_SECTION() { TRC_KERNEL_PORT_CLEAR_INTERRUPT_MASK(TRACE_ALLOC_CRITICAL_SECTION_NAME); }
655 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
657 #define TRC_HWTC_COUNT PIT.TIMER[configTICK_PIT_CHANNEL].CVAL.R
658 #define TRC_HWTC_PERIOD ((configPIT_CLOCK_HZ / configTICK_RATE_HZ) - 1U)
659 #define TRC_HWTC_FREQ_HZ configPIT_CLOCK_HZ
660 #define TRC_HWTC_DIVISOR 1
661 #define TRC_IRQ_PRIORITY_ORDER 1
663#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARMv8AR_A32)
664 extern TraceUnsignedBaseType_t cortex_a9_r5_enter_critical(
void);
665 extern void cortex_a9_r5_exit_critical(TraceUnsignedBaseType_t irq_already_masked_at_enter);
667 #define TRACE_ALLOC_CRITICAL_SECTION() TraceUnsignedBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME;
669 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = cortex_a9_r5_enter_critical(); }
671 #define TRACE_EXIT_CRITICAL_SECTION() { cortex_a9_r5_exit_critical(TRACE_ALLOC_CRITICAL_SECTION_NAME); }
673 #include <cmsis_compiler.h>
675 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
676 #define TRC_HWTC_COUNT ((uint32_t)__get_CNTPCT())
677 #define TRC_HWTC_PERIOD 0
678 #define TRC_HWTC_DIVISOR 16
679 #define TRC_HWTC_FREQ_HZ (R_GSC->CNTFID0)
680 #define TRC_IRQ_PRIORITY_ORDER 0
684 static inline uint32_t prvGetCPSR(
void)
688 __asm
volatile (
" mrs %0, cpsr" :
"=r" (ret) : );
692 #error "Only GCC Supported!"
695#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_APPLICATION_DEFINED)
697 #if !( defined (TRC_HWTC_TYPE) && defined (TRC_HWTC_COUNT) && defined (TRC_HWTC_PERIOD) && defined (TRC_HWTC_FREQ_HZ) && defined (TRC_IRQ_PRIORITY_ORDER) )
698 #error "The hardware port is not completely defined!"
701#elif (TRC_CFG_HARDWARE_PORT != TRC_HARDWARE_PORT_NOT_SET)
703 #error "TRC_CFG_HARDWARE_PORT had unsupported value!"
704 #define TRC_CFG_HARDWARE_PORT TRC_HARDWARE_PORT_NOT_SET
708#ifndef TRC_HWTC_DIVISOR
709 #define TRC_HWTC_DIVISOR 1
712#ifndef TRC_PORT_SPECIFIC_INIT
713 #define TRC_PORT_SPECIFIC_INIT()
720 #define _WIN32_WINNT 0x0600
732 #define WIN32_PORT_SAVE_WHEN_STOPPED 1
733 #define WIN32_PORT_EXIT_WHEN_STOPPED 1
737#if (TRC_CFG_HARDWARE_PORT != TRC_HARDWARE_PORT_NOT_SET)
739 #ifndef TRC_HWTC_TYPE
740 #error "TRC_HWTC_TYPE is not set!"
743 #ifndef TRC_HWTC_COUNT
744 #error "TRC_HWTC_COUNT is not set!"
747 #ifndef TRC_HWTC_PERIOD
748 #error "TRC_HWTC_PERIOD is not set!"
751 #ifndef TRC_HWTC_DIVISOR
752 #error "TRC_HWTC_DIVISOR is not set!"
755 #ifndef TRC_IRQ_PRIORITY_ORDER
756 #error "TRC_IRQ_PRIORITY_ORDER is not set!"
757 #elif (TRC_IRQ_PRIORITY_ORDER != 0) && (TRC_IRQ_PRIORITY_ORDER != 1)
758 #error "TRC_IRQ_PRIORITY_ORDER has bad value!"
761 #if (TRC_HWTC_DIVISOR < 1)
762 #error "TRC_HWTC_DIVISOR must be a non-zero positive value!"
765 #ifndef TRC_HWTC_FREQ_HZ
766 #error "TRC_HWTC_FREQ_HZ not defined!"
772#ifdef TRC_CFG_ALLOC_CRITICAL_SECTION
773#undef TRACE_ALLOC_CRITICAL_SECTION
774#define TRACE_ALLOC_CRITICAL_SECTION() TRC_CFG_ALLOC_CRITICAL_SECTION()
778#ifdef TRC_CFG_ENTER_CRITICAL_SECTION
779#undef TRACE_ENTER_CRITICAL_SECTION
780#define TRACE_ENTER_CRITICAL_SECTION() TRC_CFG_ENTER_CRITICAL_SECTION()
784#ifdef TRC_CFG_EXIT_CRITICAL_SECTION
785#undef TRACE_EXIT_CRITICAL_SECTION
786#define TRACE_EXIT_CRITICAL_SECTION() TRC_CFG_EXIT_CRITICAL_SECTION()
789#ifndef TRACE_ALLOC_CRITICAL_SECTION
790#define TRACE_ALLOC_CRITICAL_SECTION() TRC_KERNEL_PORT_ALLOC_CRITICAL_SECTION()
792#ifndef TRACE_ENTER_CRITICAL_SECTION
793#define TRACE_ENTER_CRITICAL_SECTION() TRC_KERNEL_PORT_ENTER_CRITICAL_SECTION()
795#ifndef TRACE_EXIT_CRITICAL_SECTION
796#define TRACE_EXIT_CRITICAL_SECTION() TRC_KERNEL_PORT_EXIT_CRITICAL_SECTION()