Percepio Trace Recorder v4.8.0.hotfix1
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SEGGER_RTT_Conf.h
1/*********************************************************************
2* SEGGER MICROCONTROLLER GmbH & Co. KG *
3* Solutions for real time microcontroller applications *
4**********************************************************************
5* *
6* (c) 2014 - 2016 SEGGER Microcontroller GmbH & Co. KG *
7* *
8* www.segger.com Support: support@segger.com *
9* *
10**********************************************************************
11* *
12* SEGGER RTT * Real Time Transfer for embedded targets *
13* *
14**********************************************************************
15* *
16* All rights reserved. *
17* *
18* * This software may in its unmodified form be freely redistributed *
19* in source, linkable, or executable form. *
20* * The source code may be modified, provided the source code *
21* retains the above copyright notice, this list of conditions and *
22* the following disclaimer. *
23* * Modified versions of this software in source, executable, or *
24* linkable form may not be distributed without prior consent of *
25* SEGGER. *
26* * This software may only be used for communication with SEGGER *
27* J-Link debug probes. *
28* *
29* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
30* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
31* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
32* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
33* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
34* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
35* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
36* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
37* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
38* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
39* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
40* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
41* DAMAGE. *
42* *
43**********************************************************************
44* *
45* RTT version: 6.00e *
46* *
47**********************************************************************
48----------------------------------------------------------------------
49File : SEGGER_RTT_Conf.h
50Purpose : Implementation of SEGGER real-time transfer (RTT) which
51 allows real-time communication on targets which support
52 debugger memory accesses while the CPU is running.
53Revision: $Rev: 3892 $
54---------------------------END-OF-HEADER------------------------------
55*/
56
57#ifndef SEGGER_RTT_CONF_H
58#define SEGGER_RTT_CONF_H
59
60#ifdef __IAR_SYSTEMS_ICC__
61 #include <intrinsics.h>
62#endif
63
64/*********************************************************************
65*
66* Defines, configurable
67*
68**********************************************************************
69*/
70
71#define SEGGER_RTT_MAX_NUM_UP_BUFFERS (3) // Max. number of up-buffers (T->H) available on this target (Default: 3)
72#define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (3) // Max. number of down-buffers (H->T) available on this target (Default: 3)
73
74#define BUFFER_SIZE_UP (64) // Size of the buffer for terminal output of target, up to host (Default: 1k)
75#define BUFFER_SIZE_DOWN (16) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16)
76
77#define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64)
78
79#define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0)
80
81// This can be used to place the RTT control block in the right memory range, if no found automatically.
82// This example is for NXP LPC54018, needs to be adapted for each MCU family.
83//#define SEGGER_RTT_SECTION ".data.$RAM2"
84
85//
86// Target is not allowed to perform other RTT operations while string still has not been stored completely.
87// Otherwise we would probably end up with a mixed string in the buffer.
88// If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here.
89//
90// SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4.
91// Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches.
92// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly.
93// (Higher priority = lower priority number)
94// Default value for embOS: 128u
95// Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
96// In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC
97// or define SEGGER_RTT_LOCK() to completely disable interrupts.
98//
99
100#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20)
101
102/*********************************************************************
103*
104* RTT lock configuration for SEGGER Embedded Studio,
105* Rowley CrossStudio and GCC
106*/
107#if (defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)
108 #ifdef __ARM_ARCH_6M__
109 #define SEGGER_RTT_LOCK() { \
110 unsigned int LockState; \
111 __asm volatile ("mrs %0, primask \n\t" \
112 "mov r1, $1 \n\t" \
113 "msr primask, r1 \n\t" \
114 : "=r" (LockState) \
115 : \
116 : "r1" \
117 );
118
119 #define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \
120 : \
121 : "r" (LockState) \
122 : \
123 ); \
124 }
125
126 #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__))
127 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
128 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
129 #endif
130 #define SEGGER_RTT_LOCK() { \
131 unsigned int LockState; \
132 __asm volatile ("mrs %0, basepri \n\t" \
133 "mov r1, %1 \n\t" \
134 "msr basepri, r1 \n\t" \
135 : "=r" (LockState) \
136 : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \
137 : "r1" \
138 );
139
140 #define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \
141 : \
142 : "r" (LockState) \
143 : \
144 ); \
145 }
146
147 #elif defined(__ARM_ARCH_7A__)
148 #define SEGGER_RTT_LOCK() { \
149 unsigned int LockState; \
150 __asm volatile ("mrs r1, CPSR \n\t" \
151 "mov %0, r1 \n\t" \
152 "orr r1, r1, #0xC0 \n\t" \
153 "msr CPSR_c, r1 \n\t" \
154 : "=r" (LockState) \
155 : \
156 : "r1" \
157 );
158
159 #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \
160 "mrs r1, CPSR \n\t" \
161 "bic r1, r1, #0xC0 \n\t" \
162 "and r0, r0, #0xC0 \n\t" \
163 "orr r1, r1, r0 \n\t" \
164 "msr CPSR_c, r1 \n\t" \
165 : \
166 : "r" (LockState) \
167 : "r0", "r1" \
168 ); \
169 }
170#else
171 #define SEGGER_RTT_LOCK()
172 #define SEGGER_RTT_UNLOCK()
173 #endif
174#endif
175
176/*********************************************************************
177*
178* RTT lock configuration for IAR EWARM
179*/
180#ifdef __ICCARM__
181 #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__))
182 #define SEGGER_RTT_LOCK() { \
183 unsigned int LockState; \
184 LockState = __get_PRIMASK(); \
185 __set_PRIMASK(1);
186
187 #define SEGGER_RTT_UNLOCK() __set_PRIMASK(LockState); \
188 }
189 #elif ((defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || (defined (__ARM7M__) && (__CORE__ == __ARM7M__)))
190 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
191 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
192 #endif
193 #define SEGGER_RTT_LOCK() { \
194 unsigned int LockState; \
195 LockState = __get_BASEPRI(); \
196 __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY);
197
198 #define SEGGER_RTT_UNLOCK() __set_BASEPRI(LockState); \
199 }
200 #endif
201#endif
202
203/*********************************************************************
204*
205* RTT lock configuration for IAR RX
206*/
207#ifdef __ICCRX__
208 #define SEGGER_RTT_LOCK() { \
209 unsigned long LockState; \
210 LockState = __get_interrupt_state(); \
211 __disable_interrupt();
212
213 #define SEGGER_RTT_UNLOCK() __set_interrupt_state(LockState); \
214 }
215#endif
216
217/*********************************************************************
218*
219* RTT lock configuration for KEIL ARM
220*/
221#ifdef __CC_ARM
222 #if (defined __TARGET_ARCH_6S_M)
223 #define SEGGER_RTT_LOCK() { \
224 unsigned int LockState; \
225 register unsigned char PRIMASK __asm( "primask"); \
226 LockState = PRIMASK; \
227 PRIMASK = 1u; \
228 __schedule_barrier();
229
230 #define SEGGER_RTT_UNLOCK() PRIMASK = LockState; \
231 __schedule_barrier(); \
232 }
233 #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M))
234 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
235 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
236 #endif
237 #define SEGGER_RTT_LOCK() { \
238 unsigned int LockState; \
239 register unsigned char BASEPRI __asm( "basepri"); \
240 LockState = BASEPRI; \
241 BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \
242 __schedule_barrier();
243
244 #define SEGGER_RTT_UNLOCK() BASEPRI = LockState; \
245 __schedule_barrier(); \
246 }
247 #endif
248#endif
249
250/*********************************************************************
251*
252* RTT lock configuration fallback
253*/
254#ifndef SEGGER_RTT_LOCK
255 #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts)
256#endif
257
258#ifndef SEGGER_RTT_UNLOCK
259 #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state)
260#endif
261
262#endif
263/*************************** End of file ****************************/